From cd10522093877da6a67be3a4e448b46aa5907c05 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 24 Nov 2022 16:24:45 +0800 Subject: [PATCH] clk: rockchip: fix up frac clk parent no update For some special conditions, the parent clock of fractional is not updated correctly. before clk summary: clk_spdif2_dp0_src clk_spdif2_dp0 mclk_spdif2 mclk_spdif2_dp0 clk_spdif2_dp0_frac after clk summary: clk_spdif2_dp0_src clk_spdif2_dp0_frac clk_spdif2_dp0 mclk_spdif2 mclk_spdif2_dp0 Signed-off-by: Elaine Zhang Change-Id: I9e9027774bf25f0f0ea6d8df6491a7feef4ffc48 --- drivers/clk/rockchip/clk.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 2e41b346ea31..5b2bdb33d327 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -154,6 +154,9 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb, frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx); frac->rate_change_remuxed = 1; + clk_hw_set_parent(&frac_mux->hw, + clk_hw_get_parent_by_index(&frac_mux->hw, + frac->mux_frac_idx)); } } else if (event == POST_RATE_CHANGE) { /*