From cd5289db24a7f7e879cff39bf5466e8ff19ab9ff Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 28 Mar 2018 20:04:58 +0800 Subject: [PATCH] clk: rockchip: rk3308: Set max parent rate for vop fractional divider Change-Id: I79b5b412e2952d48e83546dce69c6ce2fbe75e5b Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3308.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index 91980af9fd36..edd0f18ad727 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -21,6 +21,7 @@ #include "clk.h" #define RK3308_GRF_SOC_STATUS0 0x380 +#define RK3308_VOP_FRAC_MAX_PRATE 270000000 enum rk3308_plls { apll, dpll, vpll0, vpll1, @@ -454,7 +455,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(9), 0, RK3308_CLKGATE_CON(1), 7, GFLAGS, - &rk3308_dclk_vop_fracmux, 0), + &rk3308_dclk_vop_fracmux, RK3308_VOP_FRAC_MAX_PRATE), GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0, RK3308_CLKGATE_CON(1), 8, GFLAGS),