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drm: rockchip: dw-hdmi: Enable 3568 hdmi ddc

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Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9dd63de7a98cb70f9e40c7ee82bcfca5884b9232
This commit is contained in:
Algea Cao
2020-11-11 09:10:21 +08:00
committed by Tao Huang
parent 87649a9e7d
commit cdbb863092
1 changed files with 29 additions and 1 deletions
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30
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -57,6 +57,10 @@
#define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_GRF_SOC_CON20 0x6250
#define RK3399_HDMI_LCDC_SEL BIT(6) #define RK3399_HDMI_LCDC_SEL BIT(6)
#define RK3568_GRF_VO_CON1 0x0364
#define RK3568_HDMI_SDAIN_MSK BIT(15)
#define RK3568_HDMI_SCLIN_MSK BIT(14)
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
#define RK_HDMI_COLORIMETRY_BT2020 (HDMI_COLORIMETRY_EXTENDED + \ #define RK_HDMI_COLORIMETRY_BT2020 (HDMI_COLORIMETRY_EXTENDED + \
HDMI_EXTENDED_COLORIMETRY_BT2020) HDMI_EXTENDED_COLORIMETRY_BT2020)
@@ -69,6 +73,7 @@
*/ */
struct rockchip_hdmi_chip_data { struct rockchip_hdmi_chip_data {
int lcdsel_grf_reg; int lcdsel_grf_reg;
int ddc_en_reg;
u32 lcdsel_big; u32 lcdsel_big;
u32 lcdsel_lit; u32 lcdsel_lit;
}; };
@@ -1355,6 +1360,21 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
.ycbcr_420_allowed = true, .ycbcr_420_allowed = true,
}; };
static struct rockchip_hdmi_chip_data rk3568_chip_data = {
.lcdsel_grf_reg = -1,
.ddc_en_reg = RK3568_GRF_VO_CON1,
};
static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.mpll_cfg_420 = rockchip_mpll_cfg_420,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
.phy_data = &rk3568_chip_data,
.ycbcr_420_allowed = true,
};
static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
{ .compatible = "rockchip,rk3228-dw-hdmi", { .compatible = "rockchip,rk3228-dw-hdmi",
.data = &rk3228_hdmi_drv_data .data = &rk3228_hdmi_drv_data
@@ -1373,7 +1393,7 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
.data = &rk3399_hdmi_drv_data .data = &rk3399_hdmi_drv_data
}, },
{ .compatible = "rockchip,rk3568-dw-hdmi", { .compatible = "rockchip,rk3568-dw-hdmi",
.data = &rk3368_hdmi_drv_data //same as rk3368 .data = &rk3568_hdmi_drv_data
}, },
{}, {},
}; };
@@ -1442,6 +1462,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return ret; return ret;
} }
if (hdmi->chip_data->ddc_en_reg == RK3568_GRF_VO_CON1) {
regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
RK3568_HDMI_SCLIN_MSK,
RK3568_HDMI_SDAIN_MSK |
RK3568_HDMI_SCLIN_MSK));
}
ret = clk_prepare_enable(hdmi->phyref_clk); ret = clk_prepare_enable(hdmi->phyref_clk);
if (ret) { if (ret) {
DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",