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media: remove unused video drivers
Signed-off-by: Tao Huang <huangtao@rock-chips.com> Change-Id: Ic8d08dc1c2e41a97fd1baf874efaa05f9b5de9d9
This commit is contained in:
Tao Huang
@@ -1,26 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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config ROCK_CHIP_SOC_CAMERA
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tristate "rockchip supported soc cameras "
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default n
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menu "rockchip camera sensor interface driver"
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depends on ROCK_CHIP_SOC_CAMERA
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config ROCKCHIP_CAMERA_SENSOR_INTERFACE
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tristate "rockchip camera sensor interface driver"
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default n
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config RK30_CAMERA_ONEFRAME
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tristate "rk30_camera_oneframe"
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depends on ROCKCHIP_CAMERA_SENSOR_INTERFACE
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select SOC_CAMERA
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select VIDEOBUF_DMA_CONTIG
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default n
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config RK30_CAMERA_PINGPONG
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tristate "rk30_camera_pingpong"
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depends on ROCKCHIP_CAMERA_SENSOR_INTERFACE
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select SOC_CAMERA
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select VIDEOBUF_DMA_CONTIG
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default n
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endmenu
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@@ -1,47 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_RK30_CAMERA_PINGPONG) += rk30_camera_pingpong.o generic_sensor.o \
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gc0307.o \
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gc0308.o \
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gc0309.o \
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gc0328.o \
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gc0329.o \
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gc0312.o \
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gc2015.o \
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gc2035.o \
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gc2145.o \
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gc2155.o \
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gt2005.o \
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hm2057.o \
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hm5065.o \
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mt9p111.o \
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nt99160_2way.o \
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nt99240_2way.o \
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ov2659.o \
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ov5640.o \
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sp0838.o \
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sp2518.o \
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tp2825.o \
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adv7181.o
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obj-$(CONFIG_RK30_CAMERA_ONEFRAME) += rk30_camera_oneframe.o generic_sensor.o \
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gc0307.o \
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gc0308.o \
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gc0309.o \
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gc0312.o \
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gc0328.o \
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gc0329.o \
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gc2015.o \
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gc2035.o \
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gc2145.o \
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gc2155.o \
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gt2005.o \
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hm2057.o \
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hm5065.o \
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mt9p111.o \
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nt99160_2way.o \
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nt99240_2way.o \
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ov2659.o \
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ov5640.o \
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sp0838.o \
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sp2518.o \
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tp2825.o \
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adv7181.o
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@@ -1,12 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __HM5065_H__
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#define __HM5065_H__
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_PROPERTY 0xFFFD
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#define SEQUENCE_WAIT_MS 0xFFFE
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#define SEQUENCE_END 0xFFFC
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#endif
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@@ -1,29 +0,0 @@
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/*
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* Driver for MT9P111 CMOS Image Sensor from Aptina
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*
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MT9D112_H__
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#define __MT9D112_H__
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struct reginfo
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{
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u16 reg;
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u16 val;
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};
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_CAPTURE 0x02
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#define SEQUENCE_PREVIEW 0x03
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#define SEQUENCE_PROPERTY 0xFFFC
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#define SEQUENCE_WAIT_MS 0xFFFD
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#define SEQUENCE_WAIT_US 0xFFFE
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#define SEQUENCE_END 0xFFFF
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#endif
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@@ -1,33 +0,0 @@
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/*
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* Driver for OV5642 CMOS Image Sensor from OmniVision
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*
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MT9D113_H__
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#define __MT9D113_H__
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struct reginfo
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{
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u16 reg;
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u16 val;
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u16 reg_len;
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u16 rev;
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};
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#define WORD_LEN 0x04
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#define BYTE_LEN 0x02
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_CAPTURE 0x02
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#define SEQUENCE_PREVIEW 0x03
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#define SEQUENCE_PROPERTY 0xFFFC
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#define SEQUENCE_WAIT_MS 0xFFFD
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#define SEQUENCE_WAIT_US 0xFFFE
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#define SEQUENCE_END 0xFFFF
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#endif
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@@ -1,31 +0,0 @@
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/*
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* Driver for MT9P111 CMOS Image Sensor from Aptina
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*
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MT9M112_H__
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#define __MT9M112_H__
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struct reginfo
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{
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u8 reg;
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u16 val;
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};
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#define WORD_LEN 0x04
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#define BYTE_LEN 0x02
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_CAPTURE 0x02
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#define SEQUENCE_PREVIEW 0x03
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#define SEQUENCE_PROPERTY 0xFC
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#define SEQUENCE_WAIT_MS 0xFD
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#define SEQUENCE_WAIT_US 0xFE
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#define SEQUENCE_END 0xFF
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#endif
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@@ -1,48 +0,0 @@
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/*
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* Driver for MT9P111 CMOS Image Sensor from Aptina
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*
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MT9P111_H__
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#define __MT9P111_H__
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struct reginfo
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{
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u16 reg;
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u16 val;
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u16 reg_len;
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u16 rev;
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};
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#define WORD_LEN 0x04
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#define BYTE_LEN 0x02
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_CAPTURE 0x02
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#define SEQUENCE_PREVIEW 0x03
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#define SEQUENCE_PROPERTY 0xFFFC
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#define SEQUENCE_WAIT_MS 0xFFFD
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#define SEQUENCE_WAIT_US 0xFFFE
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#define SEQUENCE_END 0xFFFF
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/*configure register for flipe and mirror during initial*/
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#define CONFIG_SENSOR_FLIPE 0
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#define CONFIG_SENSOR_MIRROR 0
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#define CONFIG_SENSOR_MIRROR_AND_FLIPE 1
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#define CONFIG_SENSOR_NONE_FLIP_MIRROR 0
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/**adjust part parameter to solve bug******/
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#define ADJUST_FOR_720P_FALG 1
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#define ADJUST_FOR_VGA_FALG 1
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#define ADJUST_FOR_CAPTURE_FALG 1
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#define ADJUST_PCLK_FRE_FALG 1
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/**optimize code to shoten open time******/
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#define ADJUST_OPTIMIZE_TIME_FALG 1
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#endif
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@@ -1,33 +0,0 @@
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/*
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* Driver for MT9T111 CMOS Image Sensor from Aptina
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*
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MT9T111_H__
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#define __MT9T111_H__
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struct reginfo
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{
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u16 reg;
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u16 val;
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u16 reg_len;
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u16 rev;
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};
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#define WORD_LEN 0x04
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#define BYTE_LEN 0x02
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_CAPTURE 0x02
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#define SEQUENCE_PREVIEW 0x03
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#define SEQUENCE_PROPERTY 0xFFFC
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#define SEQUENCE_WAIT_MS 0xFFFD
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#define SEQUENCE_WAIT_US 0xFFFE
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#define SEQUENCE_END 0xFFFF
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#endif
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@@ -1,13 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Fujitsu camera isp chip: m6moj.
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#
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choice
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prompt "Camera Sensor attached to mv9335"
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depends on SOC_CAMERA_MV9335
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default n
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config MV9335_OV5650
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tristate "mv9335 attached ov5650"
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help
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Choose Y here if you have this this sensor and it is attach to mv9335
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endchoice
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@@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for Fujitsu isp driver
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#
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mv9335_drv-objs += mv9335.o
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obj-y += mv9335_drv.o
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@@ -1,26 +0,0 @@
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/*
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* Driver for OV5642 CMOS Image Sensor from OmniVision
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*
|
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
|
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*/
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#ifndef __OV3640_H__
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#define __OV3640_H__
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struct reginfo
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{
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u16 reg;
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u8 val;
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};
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_PROPERTY 0xFFFD
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#define SEQUENCE_WAIT_MS 0xFFFE
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#define SEQUENCE_END 0x0000
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#endif
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@@ -1,16 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __OV5640_H__
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#define __OV5640_H__
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struct reginfo
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{
|
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u16 reg;
|
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u8 val;
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};
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|
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_PROPERTY 0xFFFD
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#define SEQUENCE_WAIT_MS 0xFFFE
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#define SEQUENCE_END 0xFFFF
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#endif
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@@ -1,26 +0,0 @@
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/*
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* Driver for OV5642 CMOS Image Sensor from OmniVision
|
||||
*
|
||||
* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
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|
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#ifndef __OV5642_H__
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#define __OV5642_H__
|
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struct reginfo
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{
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u16 reg;
|
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u8 val;
|
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};
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|
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_PROPERTY 0xFFFD
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#define SEQUENCE_WAIT_MS 0xFFFE
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#define SEQUENCE_END 0xFFFF
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#endif
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@@ -1,264 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
|
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#include <mach/iomux.h>
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#include <media/soc_camera.h>
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#include <linux/android_pmem.h>
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#include <mach/rk2928_camera.h>
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#ifndef PMEM_CAM_SIZE
|
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#include "../../../arch/arm/plat-rk/rk_camera.c"
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#else
|
||||
/*****************************************************************************************
|
||||
* camera devices
|
||||
* author: ddl@rock-chips.com
|
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*****************************************************************************************/
|
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#ifdef CONFIG_VIDEO_RK29
|
||||
|
||||
static int rk_sensor_iomux(int pin)
|
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{
|
||||
iomux_set_gpio_mode(pin);
|
||||
return 0;
|
||||
}
|
||||
#define PMEM_CAM_BASE 0 //just for compile ,no meaning
|
||||
#include "../../../arch/arm/plat-rk/rk_camera.c"
|
||||
|
||||
|
||||
static u64 rockchip_device_camera_dmamask = 0xffffffffUL;
|
||||
#if RK_SUPPORT_CIF0
|
||||
static struct resource rk_camera_resource_host_0[] = {
|
||||
[0] = {
|
||||
.start = RK2928_CIF_PHYS,
|
||||
.end = RK2928_CIF_PHYS + RK2928_CIF_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_CIF,
|
||||
.end = IRQ_CIF,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
#if RK_SUPPORT_CIF1
|
||||
static struct resource rk_camera_resource_host_1[] = {
|
||||
[0] = {
|
||||
.start = RK2928_CIF_PHYS,
|
||||
.end = RK2928_CIF_PHYS+ RK2928_CIF_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_CIF,
|
||||
.end = IRQ_CIF,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
/*platform_device : */
|
||||
#if RK_SUPPORT_CIF0
|
||||
struct platform_device rk_device_camera_host_0 = {
|
||||
.name = RK29_CAM_DRV_NAME,
|
||||
.id = RK_CAM_PLATFORM_DEV_ID_0, /* This is used to put cameras on this interface */
|
||||
.num_resources = ARRAY_SIZE(rk_camera_resource_host_0),
|
||||
.resource = rk_camera_resource_host_0,
|
||||
.dev = {
|
||||
.dma_mask = &rockchip_device_camera_dmamask,
|
||||
.coherent_dma_mask = 0xffffffffUL,
|
||||
.platform_data = &rk_camera_platform_data,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if RK_SUPPORT_CIF1
|
||||
/*platform_device : */
|
||||
struct platform_device rk_device_camera_host_1 = {
|
||||
.name = RK29_CAM_DRV_NAME,
|
||||
.id = RK_CAM_PLATFORM_DEV_ID_1, /* This is used to put cameras on this interface */
|
||||
.num_resources = ARRAY_SIZE(rk_camera_resource_host_1),
|
||||
.resource = rk_camera_resource_host_1,
|
||||
.dev = {
|
||||
.dma_mask = &rockchip_device_camera_dmamask,
|
||||
.coherent_dma_mask = 0xffffffffUL,
|
||||
.platform_data = &rk_camera_platform_data,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
static void rk_init_camera_plateform_data(void)
|
||||
{
|
||||
int i,dev_idx;
|
||||
|
||||
dev_idx = 0;
|
||||
for (i=0; i<RK_CAM_NUM; i++) {
|
||||
rk_camera_platform_data.sensor_init_data[i] = &rk_init_data_sensor[i];
|
||||
if (rk_camera_platform_data.register_dev[i].device_info.name) {
|
||||
rk_camera_platform_data.register_dev[i].link_info.board_info =
|
||||
&rk_camera_platform_data.register_dev[i].i2c_cam_info;
|
||||
rk_camera_platform_data.register_dev[i].device_info.id = dev_idx;
|
||||
rk_camera_platform_data.register_dev[i].device_info.dev.platform_data =
|
||||
&rk_camera_platform_data.register_dev[i].link_info;
|
||||
dev_idx++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void rk30_camera_request_reserve_mem(void)
|
||||
{
|
||||
int i,max_resolution;
|
||||
int cam_ipp_mem=PMEM_CAMIPP_NECESSARY, cam_pmem=PMEM_CAM_NECESSARY;
|
||||
|
||||
i =0;
|
||||
max_resolution = 0x00;
|
||||
while (strstr(new_camera[i].dev.device_info.dev.init_name,"end")==NULL) {
|
||||
if (new_camera[i].resolution > max_resolution)
|
||||
max_resolution = new_camera[i].resolution;
|
||||
i++;
|
||||
}
|
||||
|
||||
if (max_resolution < PMEM_SENSOR_FULL_RESOLUTION_CIF_1)
|
||||
max_resolution = PMEM_SENSOR_FULL_RESOLUTION_CIF_1;
|
||||
if (max_resolution < PMEM_SENSOR_FULL_RESOLUTION_CIF_0)
|
||||
max_resolution = PMEM_SENSOR_FULL_RESOLUTION_CIF_0;
|
||||
|
||||
switch (max_resolution)
|
||||
{
|
||||
case 0x800000:
|
||||
default:
|
||||
{
|
||||
cam_ipp_mem = 0x800000;
|
||||
cam_pmem = 0x1900000;
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x500000:
|
||||
{
|
||||
cam_ipp_mem = 0x800000;
|
||||
cam_pmem = 0x1400000;
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x300000:
|
||||
{
|
||||
cam_ipp_mem = 0x600000;
|
||||
cam_pmem = 0xf00000;
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x200000:
|
||||
{
|
||||
cam_ipp_mem = 0x600000;
|
||||
cam_pmem = 0xc00000;
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x100000:
|
||||
{
|
||||
cam_ipp_mem = 0x600000;
|
||||
cam_pmem = 0xa00000;
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x30000:
|
||||
{
|
||||
cam_ipp_mem = 0x600000;
|
||||
cam_pmem = 0x600000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
rk_camera_platform_data.meminfo.vbase = rk_camera_platform_data.meminfo_cif1.vbase = NULL;
|
||||
#if defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF) || ((RK_SUPPORT_CIF0 && RK_SUPPORT_CIF1) == 0)
|
||||
rk_camera_platform_data.meminfo.name = "camera_ipp_mem";
|
||||
rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem",cam_ipp_mem);
|
||||
rk_camera_platform_data.meminfo.size= cam_ipp_mem;
|
||||
|
||||
memcpy(&rk_camera_platform_data.meminfo_cif1,&rk_camera_platform_data.meminfo,sizeof(struct rk29camera_mem_res));
|
||||
#else
|
||||
rk_camera_platform_data.meminfo.name = "camera_ipp_mem_0";
|
||||
rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem_0",PMEM_CAMIPP_NECESSARY_CIF_0);
|
||||
rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY_CIF_0;
|
||||
|
||||
rk_camera_platform_data.meminfo_cif1.name = "camera_ipp_mem_1";
|
||||
rk_camera_platform_data.meminfo_cif1.start =board_mem_reserve_add("camera_ipp_mem_1",PMEM_CAMIPP_NECESSARY_CIF_1);
|
||||
rk_camera_platform_data.meminfo_cif1.size= PMEM_CAMIPP_NECESSARY_CIF_1;
|
||||
#endif
|
||||
|
||||
#if PMEM_CAM_NECESSARY
|
||||
android_pmem_cam_pdata.start = board_mem_reserve_add((char*)(android_pmem_cam_pdata.name),cam_pmem);
|
||||
android_pmem_cam_pdata.size= cam_pmem;
|
||||
#endif
|
||||
|
||||
}
|
||||
static int rk_register_camera_devices(void)
|
||||
{
|
||||
int i;
|
||||
int host_registered_0,host_registered_1;
|
||||
struct rkcamera_platform_data *new_camera;
|
||||
|
||||
rk_init_camera_plateform_data();
|
||||
|
||||
host_registered_0 = 0;
|
||||
host_registered_1 = 0;
|
||||
for (i=0; i<RK_CAM_NUM; i++) {
|
||||
if (rk_camera_platform_data.register_dev[i].device_info.name) {
|
||||
if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {
|
||||
#if RK_SUPPORT_CIF0
|
||||
host_registered_0 = 1;
|
||||
#else
|
||||
printk(KERN_ERR "%s(%d) : This chip isn't support CIF0, Please user check ...\n",__FUNCTION__,__LINE__);
|
||||
#endif
|
||||
}
|
||||
|
||||
if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {
|
||||
#if RK_SUPPORT_CIF1
|
||||
host_registered_1 = 1;
|
||||
#else
|
||||
printk(KERN_ERR "%s(%d) : This chip isn't support CIF1, Please user check ...\n",__FUNCTION__,__LINE__);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
i=0;
|
||||
new_camera = rk_camera_platform_data.register_dev_new;
|
||||
if (new_camera != NULL) {
|
||||
while (strstr(new_camera->dev.device_info.dev.init_name,"end")==NULL) {
|
||||
if (new_camera->dev.link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {
|
||||
host_registered_1 = 1;
|
||||
} else if (new_camera->dev.link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {
|
||||
host_registered_0 = 1;
|
||||
}
|
||||
new_camera++;
|
||||
}
|
||||
}
|
||||
#if RK_SUPPORT_CIF0
|
||||
if (host_registered_0) {
|
||||
platform_device_register(&rk_device_camera_host_0);
|
||||
}
|
||||
#endif
|
||||
#if RK_SUPPORT_CIF1
|
||||
if (host_registered_1) {
|
||||
platform_device_register(&rk_device_camera_host_1);
|
||||
}
|
||||
#endif
|
||||
|
||||
for (i=0; i<RK_CAM_NUM; i++) {
|
||||
if (rk_camera_platform_data.register_dev[i].device_info.name) {
|
||||
platform_device_register(&rk_camera_platform_data.register_dev[i].device_info);
|
||||
}
|
||||
}
|
||||
|
||||
if (rk_camera_platform_data.sensor_register)
|
||||
(rk_camera_platform_data.sensor_register)();
|
||||
|
||||
#if PMEM_CAM_NECESSARY
|
||||
platform_device_register(&android_pmem_cam_device);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
module_init(rk_register_camera_devices);
|
||||
#endif
|
||||
|
||||
#endif //#ifdef CONFIG_VIDEO_RK
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,22 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
config CAMSYS_DRV
|
||||
tristate "camsys driver "
|
||||
default n
|
||||
|
||||
menu "RockChip camera system driver"
|
||||
depends on CAMSYS_DRV
|
||||
|
||||
source "drivers/media/video/rk_camsys/ext_flashled_drv/Kconfig"
|
||||
|
||||
config CAMSYS_MRV
|
||||
tristate "camsys driver for marvin isp "
|
||||
default n
|
||||
---help---
|
||||
|
||||
config CAMSYS_CIF
|
||||
tristate "camsys driver for cif "
|
||||
default n
|
||||
---help---
|
||||
|
||||
endmenu
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Makefile for rockchip camsys driver
|
||||
#
|
||||
obj-$(CONFIG_CAMSYS_DRV) += camsys_drv.o
|
||||
obj-$(CONFIG_CAMSYS_MRV) += camsys_marvin.o camsys_mipicsi_phy.o camsys_soc_priv.o
|
||||
obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3288.o
|
||||
obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3368.o
|
||||
obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3366.o
|
||||
obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3399.o
|
||||
obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3326.o
|
||||
obj-$(CONFIG_CAMSYS_CIF) += camsys_cif.o
|
||||
obj-y += ext_flashled_drv/
|
||||
|
||||
@@ -1,385 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#include "camsys_cif.h"
|
||||
|
||||
static const char miscdev_cif0_name[] = CAMSYS_CIF0_DEVNAME;
|
||||
static const char miscdev_cif1_name[] = CAMSYS_CIF1_DEVNAME;
|
||||
|
||||
static int camsys_cif_iomux_cb(camsys_extdev_t *extdev, void *ptr)
|
||||
{
|
||||
unsigned int cif_vol_sel;
|
||||
#if 0
|
||||
if (extdev->dev_cfg & CAMSYS_DEVCFG_FLASHLIGHT) {
|
||||
iomux_set(ISP_FLASH_TRIG);
|
||||
if (extdev->fl.fl.io != 0xffffffff) {
|
||||
iomux_set(ISP_FL_TRIG);
|
||||
}
|
||||
}
|
||||
|
||||
if (extdev->dev_cfg & CAMSYS_DEVCFG_PREFLASHLIGHT) {
|
||||
iomux_set(ISP_PRELIGHT_TRIG);
|
||||
}
|
||||
|
||||
if (extdev->dev_cfg & CAMSYS_DEVCFG_SHUTTER) {
|
||||
iomux_set(ISP_SHUTTER_OPEN);
|
||||
iomux_set(ISP_SHUTTER_TRIG);
|
||||
}
|
||||
|
||||
iomux_set(CIF0_CLKOUT);
|
||||
#endif
|
||||
|
||||
struct pinctrl *pinctrl;
|
||||
struct pinctrl_state *state;
|
||||
int retval = 0;
|
||||
char state_str[20] = {0};
|
||||
|
||||
struct device *dev = &(extdev->pdev->dev);
|
||||
|
||||
if (extdev->phy.type == CamSys_Phy_Cif) {
|
||||
if ((extdev->phy.info.cif.fmt >= CamSys_Fmt_Raw_8b) &&
|
||||
(extdev->phy.info.cif.fmt <= CamSys_Fmt_Raw_12b)) {
|
||||
|
||||
strcpy(state_str, "isp_dvp8bit");
|
||||
|
||||
}
|
||||
|
||||
if ((extdev->phy.info.cif.fmt >= CamSys_Fmt_Raw_10b) &&
|
||||
(extdev->phy.info.cif.fmt <= CamSys_Fmt_Raw_12b)) {
|
||||
strcpy(state_str, "isp_dvp10bit");
|
||||
}
|
||||
|
||||
if (extdev->phy.info.cif.fmt == CamSys_Fmt_Raw_12b) {
|
||||
strcpy(state_str, "isp_dvp12bit");
|
||||
|
||||
}
|
||||
} else {
|
||||
strcpy(state_str, "default");
|
||||
}
|
||||
|
||||
/*mux CIF0_CLKOUT*/
|
||||
|
||||
pinctrl = devm_pinctrl_get(dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
camsys_err("%s:Get pinctrl failed!\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
state = pinctrl_lookup_state(pinctrl,
|
||||
state_str);
|
||||
if (IS_ERR(state)) {
|
||||
dev_err(dev,
|
||||
"%s:could not get %s pinstate\n",
|
||||
__func__, state_str);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!IS_ERR(state)) {
|
||||
retval = pinctrl_select_state(pinctrl, state);
|
||||
if (retval) {
|
||||
dev_err(dev,
|
||||
"%s:could not set %s pins\n",
|
||||
__func__, state_str);
|
||||
return -1;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/*set 1.8v vol domain for rk32*/
|
||||
__raw_writel(((1<<1)|(1<<(1+16))), RK_GRF_VIRT+0x0380);
|
||||
__raw_writel(0xffffffff, RK_GRF_VIRT+0x01d4);
|
||||
|
||||
/*set cif vol domain*/
|
||||
if (extdev->phy.type == CamSys_Phy_Cif) {
|
||||
|
||||
#if 0
|
||||
if (!IS_ERR_OR_NULL(extdev->dovdd.ldo)) {
|
||||
if (extdev->dovdd.max_uv >= 25000000) {
|
||||
__raw_writel(((1<<1)|(1<<(1+16))),
|
||||
RK30_GRF_BASE+0x018c);
|
||||
} else {
|
||||
__raw_writel((1<<(1+16)), RK30_GRF_BASE+0x018c);
|
||||
}
|
||||
} else {
|
||||
__raw_writel(((1<<1)|(1<<(1+16))),
|
||||
RK30_GRF_BASE+0x018c);
|
||||
}
|
||||
#else
|
||||
|
||||
/*set 1.8v vol domain*/
|
||||
__raw_writel(((1<<1)|(1<<(1+16))), RK_GRF_VIRT+0x0380);
|
||||
#endif
|
||||
|
||||
/*set driver strength*/
|
||||
/* __raw_writel(0xffffffff, RK_GRF_VIRT+0x01dc);*/
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int camsys_cif_clkin_cb(void *ptr, unsigned int on)
|
||||
{
|
||||
camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
|
||||
camsys_cif_clk_t *clk = (camsys_cif_clk_t *)camsys_dev->clk;
|
||||
|
||||
spin_lock(&clk->lock);
|
||||
if (on && !clk->in_on) {
|
||||
clk_prepare_enable(clk->aclk_cif);
|
||||
clk_prepare_enable(clk->hclk_cif);
|
||||
clk_prepare_enable(clk->cif_clk_in);
|
||||
|
||||
clk->in_on = true;
|
||||
camsys_trace(1, "%s clock in turn on",
|
||||
dev_name(camsys_dev->miscdev.this_device));
|
||||
} else if (!on && clk->in_on) {
|
||||
clk_disable_unprepare(clk->hclk_cif);
|
||||
clk_disable_unprepare(clk->cif_clk_in);
|
||||
clk_disable_unprepare(clk->pd_cif);
|
||||
clk->in_on = false;
|
||||
camsys_trace(1, "%s clock in turn off",
|
||||
dev_name(camsys_dev->miscdev.this_device));
|
||||
}
|
||||
spin_unlock(&clk->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_cif_clkout_cb(void *ptr, unsigned int on, unsigned int clkin)
|
||||
{
|
||||
camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
|
||||
camsys_cif_clk_t *clk = (camsys_cif_clk_t *)camsys_dev->clk;
|
||||
struct clk *cif_clk_out_div;
|
||||
|
||||
spin_lock(&clk->lock);
|
||||
if (on && (clk->out_on != on)) {
|
||||
clk_prepare_enable(clk->cif_clk_out);
|
||||
clk_set_rate(clk->cif_clk_out, clkin);
|
||||
|
||||
clk->out_on = on;
|
||||
camsys_trace(1, "%s clock out(rate: %dHz) turn on",
|
||||
dev_name(camsys_dev->miscdev.this_device),
|
||||
clk->out_on);
|
||||
} else if (!on && clk->out_on) {
|
||||
if (strcmp(dev_name(camsys_dev->miscdev.this_device),
|
||||
miscdev_cif1_name) == 0) {
|
||||
cif_clk_out_div = clk_get(NULL, "cif1_out_div");
|
||||
} else{
|
||||
cif_clk_out_div = clk_get(NULL, "cif0_out_div");
|
||||
if (IS_ERR_OR_NULL(cif_clk_out_div)) {
|
||||
cif_clk_out_div =
|
||||
clk_get(NULL, "cif_out_div");
|
||||
}
|
||||
}
|
||||
|
||||
if (!IS_ERR_OR_NULL(cif_clk_out_div)) {
|
||||
clk_set_parent(clk->cif_clk_out, cif_clk_out_div);
|
||||
clk_put(cif_clk_out_div);
|
||||
} else {
|
||||
camsys_warn("%s clock out may be not off!",
|
||||
dev_name(camsys_dev->miscdev.this_device));
|
||||
}
|
||||
clk_disable_unprepare(clk->cif_clk_out);
|
||||
clk->out_on = 0;
|
||||
|
||||
camsys_trace(1, "%s clock out turn off",
|
||||
dev_name(camsys_dev->miscdev.this_device));
|
||||
}
|
||||
spin_unlock(&clk->lock);
|
||||
|
||||
/* __raw_writel(0x00, CRU_PCLK_REG30+RK30_CRU_BASE);*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t camsys_cif_irq(int irq, void *data)
|
||||
{
|
||||
camsys_dev_t *camsys_dev = (camsys_dev_t *)data;
|
||||
camsys_irqstas_t *irqsta;
|
||||
camsys_irqpool_t *irqpool;
|
||||
unsigned int intsta, frmsta;
|
||||
|
||||
intsta = __raw_readl(camsys_dev->devmems.registermem->vir_base +
|
||||
CIF_INITSTA);
|
||||
frmsta = __raw_readl(camsys_dev->devmems.registermem->vir_base +
|
||||
CIF_FRAME_STATUS);
|
||||
printk("get oneframe, intsta = 0x%x \n", intsta);
|
||||
|
||||
if (intsta & 0x200) {
|
||||
__raw_writel(0x200,
|
||||
camsys_dev->devmems.registermem->vir_base +
|
||||
CIF_INITSTA);
|
||||
__raw_writel(0xf000,
|
||||
camsys_dev->devmems.registermem->vir_base +
|
||||
CIF_CTRL);
|
||||
}
|
||||
|
||||
if (intsta &0x01) {
|
||||
__raw_writel(0x01,
|
||||
camsys_dev->devmems.registermem->vir_base +
|
||||
CIF_INITSTA);
|
||||
__raw_writel(0x02,
|
||||
camsys_dev->devmems.registermem->vir_base +
|
||||
CIF_FRAME_STATUS);
|
||||
__raw_writel(0xf001,
|
||||
camsys_dev->devmems.registermem->vir_base +
|
||||
CIF_CTRL);
|
||||
}
|
||||
|
||||
spin_lock(&camsys_dev->irq.lock);
|
||||
list_for_each_entry(irqpool, &camsys_dev->irq.irq_pool, list) {
|
||||
spin_lock(&irqpool->lock);
|
||||
if (!list_empty(&irqpool->deactive)) {
|
||||
irqsta = list_first_entry
|
||||
(&irqpool->deactive, camsys_irqstas_t, list);
|
||||
irqsta->sta.mis = intsta;
|
||||
irqsta->sta.ris = intsta;
|
||||
list_del_init(&irqsta->list);
|
||||
list_add_tail(&irqsta->list, &irqpool->active);
|
||||
irqsta = list_first_entry
|
||||
(&irqpool->active, camsys_irqstas_t, list);
|
||||
/*wake_up_all(&camsys_dev->irq.irq_done);*/
|
||||
wake_up(&irqpool->done);
|
||||
}
|
||||
spin_unlock(&irqpool->lock);
|
||||
}
|
||||
spin_unlock(&camsys_dev->irq.lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int camsys_cif_remove(struct platform_device *pdev)
|
||||
{
|
||||
camsys_dev_t *camsys_dev = platform_get_drvdata(pdev);
|
||||
camsys_cif_clk_t *cif_clk;
|
||||
|
||||
if (camsys_dev->clk != NULL) {
|
||||
cif_clk = (camsys_cif_clk_t *)camsys_dev->clk;
|
||||
if (cif_clk->out_on)
|
||||
camsys_cif_clkout_cb(camsys_dev->clk, 0, 0);
|
||||
if (cif_clk->in_on)
|
||||
camsys_cif_clkin_cb(camsys_dev->clk, 0);
|
||||
|
||||
if (cif_clk->pd_cif)
|
||||
clk_put(cif_clk->pd_cif);
|
||||
if (cif_clk->aclk_cif)
|
||||
clk_put(cif_clk->aclk_cif);
|
||||
if (cif_clk->hclk_cif)
|
||||
clk_put(cif_clk->hclk_cif);
|
||||
if (cif_clk->cif_clk_in)
|
||||
clk_put(cif_clk->cif_clk_in);
|
||||
if (cif_clk->cif_clk_out)
|
||||
clk_put(cif_clk->cif_clk_out);
|
||||
|
||||
kfree(cif_clk);
|
||||
cif_clk = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int camsys_cif_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev)
|
||||
{
|
||||
int err = 0;
|
||||
camsys_cif_clk_t *cif_clk;
|
||||
|
||||
/*Irq init*/
|
||||
err = request_irq(camsys_dev->irq.irq_id,
|
||||
camsys_cif_irq, 0, CAMSYS_CIF_IRQNAME,
|
||||
camsys_dev);
|
||||
if (err) {
|
||||
camsys_err("request irq for %s failed", CAMSYS_CIF_IRQNAME);
|
||||
goto end;
|
||||
}
|
||||
|
||||
/*Clk and Iomux init*/
|
||||
cif_clk = kzalloc(sizeof(camsys_cif_clk_t), GFP_KERNEL);
|
||||
if (cif_clk == NULL) {
|
||||
camsys_err("Allocate camsys_cif_clk_t failed!");
|
||||
err = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
|
||||
if (strcmp(dev_name(&pdev->dev), CAMSYS_PLATFORM_CIF1_NAME) == 0) {
|
||||
cif_clk->aclk_cif = devm_clk_get(&pdev->dev, "g_aclk_vip");
|
||||
cif_clk->hclk_cif = devm_clk_get(&pdev->dev, "g_hclk_vip");
|
||||
cif_clk->cif_clk_in = devm_clk_get(&pdev->dev, "g_pclkin_cif");
|
||||
cif_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_cif_out");
|
||||
spin_lock_init(&cif_clk->lock);
|
||||
cif_clk->in_on = false;
|
||||
cif_clk->out_on = false;
|
||||
} else {
|
||||
cif_clk->aclk_cif = devm_clk_get(&pdev->dev, "g_aclk_vip");
|
||||
cif_clk->hclk_cif = devm_clk_get(&pdev->dev, "g_hclk_vip");
|
||||
cif_clk->cif_clk_in = devm_clk_get(&pdev->dev, "g_pclkin_ci");
|
||||
cif_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_cif_out");
|
||||
spin_lock_init(&cif_clk->lock);
|
||||
cif_clk->in_on = false;
|
||||
cif_clk->out_on = false;
|
||||
}
|
||||
|
||||
/*
|
||||
*clk_prepare_enable(cif_clk->aclk_cif);
|
||||
clk_prepare_enable(cif_clk->hclk_cif);
|
||||
clk_prepare_enable(cif_clk->cif_clk_in);
|
||||
clk_prepare_enable(cif_clk->cif_clk_out);
|
||||
*/
|
||||
|
||||
camsys_dev->clk = (void *)cif_clk;
|
||||
camsys_dev->clkin_cb = camsys_cif_clkin_cb;
|
||||
camsys_dev->clkout_cb = camsys_cif_clkout_cb;
|
||||
camsys_dev->iomux = camsys_cif_iomux_cb;
|
||||
|
||||
/*Misc device init*/
|
||||
camsys_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
|
||||
if (strcmp(dev_name(&pdev->dev), CAMSYS_PLATFORM_CIF1_NAME) == 0) {
|
||||
camsys_dev->miscdev.name = miscdev_cif1_name;
|
||||
camsys_dev->miscdev.nodename = miscdev_cif1_name;
|
||||
} else {
|
||||
camsys_dev->miscdev.name = miscdev_cif0_name;
|
||||
camsys_dev->miscdev.nodename = miscdev_cif0_name;
|
||||
}
|
||||
camsys_dev->miscdev.fops = &camsys_fops;
|
||||
err = misc_register(&camsys_dev->miscdev);
|
||||
if (err < 0) {
|
||||
camsys_trace(1,
|
||||
"Register /dev/%s misc device failed",
|
||||
camsys_dev->miscdev.name);
|
||||
goto misc_register_failed;
|
||||
} else {
|
||||
camsys_trace(1,
|
||||
"Register /dev/%s misc device success",
|
||||
camsys_dev->miscdev.name);
|
||||
}
|
||||
|
||||
/*Variable init*/
|
||||
if (strcmp(dev_name(&pdev->dev), CAMSYS_PLATFORM_CIF1_NAME) == 0) {
|
||||
camsys_dev->dev_id = CAMSYS_DEVID_CIF_1;
|
||||
} else {
|
||||
camsys_dev->dev_id = CAMSYS_DEVID_CIF_0;
|
||||
}
|
||||
camsys_dev->platform_remove = camsys_cif_remove;
|
||||
|
||||
return 0;
|
||||
|
||||
misc_register_failed:
|
||||
if (!IS_ERR(camsys_dev->miscdev.this_device)) {
|
||||
misc_deregister(&camsys_dev->miscdev);
|
||||
}
|
||||
|
||||
if (cif_clk) {
|
||||
|
||||
if (cif_clk->pd_cif)
|
||||
clk_put(cif_clk->pd_cif);
|
||||
if (cif_clk->aclk_cif)
|
||||
clk_put(cif_clk->aclk_cif);
|
||||
if (cif_clk->hclk_cif)
|
||||
clk_put(cif_clk->hclk_cif);
|
||||
if (cif_clk->cif_clk_in)
|
||||
clk_put(cif_clk->cif_clk_in);
|
||||
if (cif_clk->cif_clk_out)
|
||||
clk_put(cif_clk->cif_clk_out);
|
||||
|
||||
kfree(cif_clk);
|
||||
cif_clk = NULL;
|
||||
}
|
||||
|
||||
end:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(camsys_cif_probe_cb);
|
||||
|
||||
@@ -1,64 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __CAMSYS_CIF_H__
|
||||
#define __CAMSYS_CIF_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
#define CAMSYS_CIF_IRQNAME "CifIrq"
|
||||
|
||||
|
||||
#define CIF_BASE 0x00
|
||||
#define CIF_CTRL (CIF_BASE)
|
||||
#define CIF_INITSTA (CIF_BASE+0x08)
|
||||
#define CIF_FRAME_STATUS (CIF_BASE+0x60)
|
||||
#define CIF_LAST_LINE (CIF_BASE+0x68)
|
||||
#define CIF_LAST_PIX (CIF_BASE+0x6c)
|
||||
#define CRU_PCLK_REG30 0xbc
|
||||
|
||||
|
||||
#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) \
|
||||
|| defined(CONFIG_ARCH_ROCKCHIP)
|
||||
/*GRF_IO_CON3 0x100*/
|
||||
#define CIF_DRIVER_STRENGTH_2MA (0x00 << 12)
|
||||
#define CIF_DRIVER_STRENGTH_4MA (0x01 << 12)
|
||||
#define CIF_DRIVER_STRENGTH_8MA (0x02 << 12)
|
||||
#define CIF_DRIVER_STRENGTH_12MA (0x03 << 12)
|
||||
#define CIF_DRIVER_STRENGTH_MASK (0x03 << 28)
|
||||
|
||||
/*GRF_IO_CON4 0x104*/
|
||||
#define CIF_CLKOUT_AMP_3V3 (0x00 << 10)
|
||||
#define CIF_CLKOUT_AMP_1V8 (0x01 << 10)
|
||||
#define CIF_CLKOUT_AMP_MASK (0x01 << 26)
|
||||
|
||||
#define write_grf_reg(addr, val) \
|
||||
__raw_writel(val, addr+RK_GRF_VIRT)
|
||||
#define read_grf_reg(addr) \
|
||||
__raw_readl(addr+RK_GRF_VIRT)
|
||||
#define mask_grf_reg(addr, msk, val) \
|
||||
write_grf_reg(addr, (val)|((~(msk))&read_grf_reg(addr)))
|
||||
#else
|
||||
#define write_grf_reg(addr, val)
|
||||
#define read_grf_reg(addr) 0
|
||||
#define mask_grf_reg(addr, msk, val)
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct camsys_cif_clk_s {
|
||||
struct clk *pd_cif;
|
||||
struct clk *aclk_cif;
|
||||
struct clk *hclk_cif;
|
||||
struct clk *cif_clk_in;
|
||||
bool in_on;
|
||||
|
||||
struct clk *cif_clk_out;
|
||||
unsigned int out_on;
|
||||
|
||||
spinlock_t lock;
|
||||
} camsys_cif_clk_t;
|
||||
|
||||
|
||||
int camsys_cif_probe_cb(
|
||||
struct platform_device *pdev, camsys_dev_t *camsys_dev);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,93 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RKCAMSYS_GPIO_H__
|
||||
#define __RKCAMSYS_GPIO_H__
|
||||
|
||||
#if defined(CONFIG_ARCH_ROCKCHIP)
|
||||
#define RK30_PIN0_PA0 (0)
|
||||
#define NUM_GROUP (32)
|
||||
#define GPIO_BANKS (9)
|
||||
#endif
|
||||
extern unsigned int CHIP_TYPE;
|
||||
|
||||
static inline unsigned int camsys_gpio_group_pin(unsigned char *io_name)
|
||||
{
|
||||
char *pin_char = NULL;
|
||||
int pin = -1;
|
||||
|
||||
if (strstr(io_name, "PA")) {
|
||||
pin_char = strstr(io_name, "PA");
|
||||
pin_char += 2;
|
||||
pin = *pin_char - 0x30;
|
||||
} else if (strstr(io_name, "PB")) {
|
||||
pin_char = strstr(io_name, "PB");
|
||||
pin_char += 2;
|
||||
pin = *pin_char - 0x30;
|
||||
pin += 8;
|
||||
} else if (strstr(io_name, "PC")) {
|
||||
pin_char = strstr(io_name, "PC");
|
||||
pin_char += 2;
|
||||
pin = *pin_char - 0x30;
|
||||
pin += 16;
|
||||
} else if (strstr(io_name, "PD")) {
|
||||
pin_char = strstr(io_name, "PD");
|
||||
pin_char += 2;
|
||||
pin = *pin_char - 0x30;
|
||||
pin += 24;
|
||||
}
|
||||
return pin;
|
||||
}
|
||||
|
||||
static inline unsigned int camsys_gpio_group(unsigned char *io_name)
|
||||
{
|
||||
unsigned int group = 0;
|
||||
|
||||
if (strstr(io_name, "PIN0"))
|
||||
group = 0;
|
||||
else if (strstr(io_name, "PIN1"))
|
||||
group = 1;
|
||||
else if (strstr(io_name, "PIN2"))
|
||||
group = 2;
|
||||
else if (strstr(io_name, "PIN3"))
|
||||
group = 3;
|
||||
else if (strstr(io_name, "PIN4"))
|
||||
group = 4;
|
||||
else if (strstr(io_name, "PIN5"))
|
||||
group = 5;
|
||||
else if (strstr(io_name, "PIN6"))
|
||||
group = 6;
|
||||
else if (strstr(io_name, "PIN7"))
|
||||
group = 7;
|
||||
else if (strstr(io_name, "PIN8"))
|
||||
group = 8;
|
||||
return group;
|
||||
}
|
||||
|
||||
static inline unsigned int camsys_gpio_get(unsigned char *io_name)
|
||||
{
|
||||
unsigned int gpio = 0;
|
||||
unsigned int group = 0;
|
||||
int group_pin = 0;
|
||||
#if (defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) ||\
|
||||
defined(CONFIG_ARCH_RK319X) || defined(CONFIG_ARCH_ROCKCHIP))
|
||||
if (strstr(io_name, "RK30_")) {
|
||||
gpio = RK30_PIN0_PA0;
|
||||
group = camsys_gpio_group(io_name);
|
||||
group_pin = camsys_gpio_group_pin(io_name);
|
||||
if (group_pin == -1)
|
||||
gpio = 0xffffffff;
|
||||
else {
|
||||
if (group >= GPIO_BANKS)
|
||||
gpio = 0xffffffff;
|
||||
else
|
||||
gpio += group * NUM_GROUP + group_pin;
|
||||
}
|
||||
/* gpio0_D is unavailable on rk3288. */
|
||||
if (!strstr(io_name, "PIN0") && 3288 == CHIP_TYPE)
|
||||
gpio -= 8;
|
||||
}
|
||||
#endif
|
||||
return gpio;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,507 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RKCAMSYS_INTERNAL_H__
|
||||
#define __RKCAMSYS_INTERNAL_H__
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/fcntl.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/rockchip/cpu.h>
|
||||
#include <linux/rockchip/grf.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/rockchip/cpu.h>
|
||||
#include <media/camsys_head.h>
|
||||
#include <linux/rockchip-iovmm.h>
|
||||
|
||||
/*
|
||||
* C A M S Y S D R I V E R V E R S I O N
|
||||
*
|
||||
*v0.0.1:
|
||||
* 1) test version;
|
||||
*v0.0.2:
|
||||
* 1) add mipi csi phy;
|
||||
*v0.0.3:
|
||||
* 1) add support cif phy for marvin;
|
||||
*v0.0.4:
|
||||
* 1) add clock information in struct camsys_devio_name_s;
|
||||
*v0.0.5:
|
||||
* 1) set isp clock at 32MHz;
|
||||
*v0.0.6:
|
||||
* 1) iomux d0 d1 for cif phy raw10 in rk319x after i2c operated;
|
||||
* 2) check mis value in camsys_irq_connect;
|
||||
3) add soft rest callback;
|
||||
*v0.7.0:
|
||||
1) check extdev is activate or not before delete from
|
||||
camsys_dev active list;
|
||||
*v0.8.0:
|
||||
1) fix deregister a unregister extdev oops
|
||||
in camsys_extdev_deregister;
|
||||
*v0.9.0: 1) set isp freq to 210M
|
||||
*v0.a.0:
|
||||
1) fix camsys_i2c_write and camsys_i2c_write
|
||||
can't support reg_size=0;
|
||||
*v0.b.0:
|
||||
1) control ddr freq by marvin self other than by clk unit.
|
||||
*v0.c.0:
|
||||
* 1) add flash_trigger_out control
|
||||
*v0.d.0:
|
||||
* 1) add Isp_SoftRst for rk3288;
|
||||
*v0.e.0:
|
||||
* 1) isp_clk 208.8M for 1lane, isp_clk 416.6M for 2lane;
|
||||
*v0.f.0:
|
||||
1) mi_mis register may read erro, this may cause
|
||||
mistaken mi frame_end irqs.
|
||||
*v0.0x10.0:
|
||||
1) add flash_prelight control.
|
||||
*v0.0x11.0:
|
||||
1) raise qos of isp up to the same as lcdc.
|
||||
*v0.0x12.0:
|
||||
1) support iommu.
|
||||
*v0.0x13.0:
|
||||
1) camsys_extdev_register return failed when this
|
||||
dev_id has been registered;
|
||||
2) add support JPG irq connect;
|
||||
*v0.0x14.0:
|
||||
1) camsys_extdev_register return -EBUSY when this
|
||||
dev_id has been registered;
|
||||
*v0.0x15.0:
|
||||
1) check extdev name when dev_id has been registered;
|
||||
*v0.0x16.0:
|
||||
1) enable or disable IOMMU just depending
|
||||
on CONFIG_ROCKCHIP_IOMMU.
|
||||
*v0.0x17.0:
|
||||
1) isp iommu status depend on vpu iommu status.
|
||||
*v0.0x18.0:
|
||||
1) add flashlight RT8547 driver
|
||||
2) support torch mode
|
||||
*v0.0x19.0:
|
||||
1) set CONFIG_CAMSYS_DRV disable as default,
|
||||
enable in defconfig file if needed.
|
||||
*v0.0x1a.0:
|
||||
1) vpu_node changed from "vpu_service" to "rockchip,vpu_sub"
|
||||
*v0.0x1b.0:
|
||||
1) use of_find_node_by_name to get vpu node
|
||||
instead of of_find_compatible_node
|
||||
*v0.0x1c.0:
|
||||
1) support rk3368.
|
||||
*v0.0x1d.0:
|
||||
1) enable aclk_rga for rk3368, otherwise,
|
||||
isp reset will cause system halted.
|
||||
*v0.0x1e.0:
|
||||
1) dts remove aclk_rga, change aclk_isp
|
||||
from <clk_gates17 0> to <&clk_gates16 0>.
|
||||
2) add rl3369 pd_isp enable/disable.
|
||||
*v0.0x1f.0:
|
||||
1) GPIO(gpio7 GPIO_B5) is EBUSY
|
||||
when register after factory reset,
|
||||
but after power on ,it's normal.
|
||||
*v0.0x20.0:
|
||||
1) rk3368 camera: hold vio0 noc clock during the camera work,
|
||||
fixed isp iommu stall failed.
|
||||
*v0.0x21.0:
|
||||
1) add isp-dvp-d4d11 iomux support.
|
||||
*v0.0x21.1:
|
||||
1) support rk3368-sheep kernel ver4.4.
|
||||
*v0.0x21.2:
|
||||
1) support rk3399.
|
||||
*v0.0x21.3:
|
||||
1) some modifications.
|
||||
*v0.0x21.4:
|
||||
1) modify for rk3399.
|
||||
*v0.0x21.5:
|
||||
1) modify for mipiphy hsfreqrange.
|
||||
*v0.0x21.6:
|
||||
1) support drm iommu.
|
||||
*v0.0x21.7:
|
||||
* 1) remove memset function wrong called code.
|
||||
*v0.0x21.8:
|
||||
* 1) flash module exist risk, fix up it.
|
||||
*v0.0x21.9:
|
||||
1) fix drm iommu crash.
|
||||
if process cameraserver was died during streaming, iommu resource
|
||||
was not released correctly. when cameraserver was recovered and
|
||||
streaming again, iommu resource may be conflicted.
|
||||
*v0.0x21.0xa:
|
||||
1) clock clk_vio0_noc would cause mipi lcdc no display on 3368h, remove it.
|
||||
*v0.0x21.0xb:
|
||||
1) some log is boring, so set print level more high.
|
||||
*v0.0x21.0xc:
|
||||
1) support rk3288.
|
||||
*v0.0x21.0xd:
|
||||
1) modify mipiphy_hsfreqrange for 3368.
|
||||
*v0.0x21.0xe
|
||||
1) correct mipiphy_hsfreqrange of 3368.
|
||||
2) add csi-phy timing setting for 3368.
|
||||
*v0.0x21.0xf:
|
||||
1) add reference count for marvin.
|
||||
*v0.0x22.0:
|
||||
1) delete node in irqpool list when thread disconnect.
|
||||
*v0.0x22.1:
|
||||
1) gpio0_D is unavailable on rk3288 with current pinctrl driver.
|
||||
*v0.0x22.2:
|
||||
1) modify the condition of DRM iommu, which makes code more readable
|
||||
by using of_parse_phandle to check whether the "iommus" phandle exists
|
||||
in the isp device node.
|
||||
*v0.0x22.3:
|
||||
1) switch TX1/RX1 D-PHY of rk3288/3399 to RX status before
|
||||
it's initialization to avoid conflicting with sensor output.
|
||||
*v0.0x22.4:
|
||||
1) enable SYS_STATUS_ISP status set.
|
||||
*v0.0x22.5:
|
||||
1) gpio base start from 1000,adapt to it.
|
||||
*v0.0x22.6:
|
||||
1) revert v0.0x22.3.
|
||||
*v0.0x22.7:
|
||||
1) read MRV_MIPI_FRAME register in camsys_mrv_irq, and pass the value
|
||||
fs_id and fe_id into isp library.
|
||||
*v0.0x22.8:
|
||||
1) 3399 power management is wrong, correct it.
|
||||
*v0.0x23.0:
|
||||
1) replace current->pid with irqsta->pid.
|
||||
*v0.0x24.0:
|
||||
1) function is the same as commit in v0.0x22.3 but now is better way.
|
||||
*v0.0x25.0:
|
||||
1) support px30.
|
||||
*v0.0x26.0:
|
||||
1) v0.0x21.9 may not fix all the case of iommu issue caused by the
|
||||
unexpected termination of process cameraserver, so we force to release
|
||||
all iommu resource in |.release| of fops aganin if needed.
|
||||
*v0.0x27.0:
|
||||
1) revert v0.0x22.5.
|
||||
*v0.0x28.0:
|
||||
1) fix isp soft reset failure for rk3326.
|
||||
reset on too high aclk rate will result in bus dead, so we reduce the aclk
|
||||
before reset and then recover it after reset.
|
||||
*v0.0x28.1:
|
||||
1) another reasonable solution of isp soft reset failure for rk3326.
|
||||
reset on too high isp_clk rate will result in bus dead.
|
||||
The signoff isp_clk rate is 350M, and the recommended rate
|
||||
on reset from IC is NOT greater than 300M.
|
||||
*v0.0x29.0:
|
||||
1) fix camera mipi phy config for rk3288.
|
||||
CSIHOST_PHY_SHUTDOWNZ and CSIHOST_DPHY_RSTZ is
|
||||
csi host control interface;so DPHY_RX1_SRC_SEL_MASK
|
||||
should be set DPHY_RX1_SRC_SEL_CSI.
|
||||
*v0.0x30.0:
|
||||
1) rk3326 and other platform power management implementation.
|
||||
*/
|
||||
|
||||
#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x30, 0)
|
||||
|
||||
#define CAMSYS_PLATFORM_DRV_NAME "RockChip-CamSys"
|
||||
#define CAMSYS_PLATFORM_MARVIN_NAME "Platform_MarvinDev"
|
||||
#define CAMSYS_PLATFORM_CIF0_NAME "Platform_Cif0Dev"
|
||||
#define CAMSYS_PLATFORM_CIF1_NAME "Platform_Cif1Dev"
|
||||
|
||||
#define CAMSYS_REGISTER_RES_NAME "CamSys_RegMem"
|
||||
#define CAMSYS_REGISTER_MIPIPHY_RES_NAME "CamSys_RegMem_MipiPhy"
|
||||
#define CAMSYS_IRQ_RES_NAME "CamSys_Irq"
|
||||
|
||||
#define CAMSYS_REGISTER_MEM_NAME CAMSYS_REGISTER_RES_NAME
|
||||
#define CAMSYS_I2C_MEM_NAME "CamSys_I2cMem"
|
||||
#define CAMSYS_MIPIPHY_MEM_NAME \
|
||||
CAMSYS_REGISTER_MIPIPHY_RES_NAME
|
||||
|
||||
#define CAMSYS_NAMELEN_MIN(a) \
|
||||
((strlen(a) > (CAMSYS_NAME_LEN-1))?(CAMSYS_NAME_LEN-1):strlen(a))
|
||||
#define CAMSYS_IRQPOOL_NUM 128
|
||||
#define CAMSYS_DMA_BUF_MAX_NUM 32
|
||||
|
||||
extern unsigned int camsys_debug;
|
||||
|
||||
#define camsys_trace(level, msg, ...) \
|
||||
do { \
|
||||
if (camsys_debug >= level) \
|
||||
printk("D%d:%s(%d): " msg "\n", level,\
|
||||
__FUNCTION__, __LINE__, ## __VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
#define camsys_warn(msg, ...) \
|
||||
printk(KERN_ERR "W:%s(%d): " msg "\n", __FUNCTION__,\
|
||||
__LINE__, ## __VA_ARGS__)
|
||||
#define camsys_err(msg, ...) \
|
||||
printk(KERN_ERR "E:%s(%d): " msg "\n", __FUNCTION__,\
|
||||
__LINE__, ## __VA_ARGS__)
|
||||
|
||||
typedef struct camsys_irqstas_s {
|
||||
camsys_irqsta_t sta;
|
||||
struct list_head list;
|
||||
} camsys_irqstas_t;
|
||||
|
||||
typedef struct camsys_irqpool_s {
|
||||
pid_t pid;
|
||||
unsigned int timeout;/* us */
|
||||
unsigned int mis;
|
||||
unsigned int icr;
|
||||
spinlock_t lock;/* lock for list */
|
||||
camsys_irqstas_t pool[CAMSYS_IRQPOOL_NUM];
|
||||
struct list_head active;
|
||||
struct list_head deactive;
|
||||
|
||||
struct list_head list;
|
||||
|
||||
wait_queue_head_t done;
|
||||
} camsys_irqpool_t;
|
||||
|
||||
typedef struct camsys_irq_s {
|
||||
unsigned int irq_id;
|
||||
/* lock for timeout and irq_connect in ioctl */
|
||||
spinlock_t lock;
|
||||
struct list_head irq_pool;
|
||||
} camsys_irq_t;
|
||||
|
||||
typedef struct camsys_meminfo_s {
|
||||
unsigned char name[32];
|
||||
unsigned long phy_base;
|
||||
unsigned long vir_base;
|
||||
unsigned int size;
|
||||
unsigned int vmas;
|
||||
struct list_head list;
|
||||
} camsys_meminfo_t;
|
||||
|
||||
typedef struct camsys_devmems_s {
|
||||
camsys_meminfo_t *registermem;
|
||||
camsys_meminfo_t *i2cmem;
|
||||
struct list_head memslist;
|
||||
} camsys_devmems_t;
|
||||
|
||||
typedef struct camsys_regulator_s {
|
||||
struct regulator *ldo;
|
||||
int min_uv;
|
||||
int max_uv;
|
||||
} camsys_regulator_t;
|
||||
|
||||
typedef struct camsys_gpio_s {
|
||||
unsigned int io;
|
||||
unsigned int active;
|
||||
} camsys_gpio_t;
|
||||
typedef struct camsys_flash_s {
|
||||
camsys_gpio_t fl;
|
||||
camsys_gpio_t fl_en;
|
||||
void *ext_fsh_dev;
|
||||
} camsys_flash_t;
|
||||
typedef struct camsys_extdev_s {
|
||||
unsigned char dev_name[CAMSYS_NAME_LEN];
|
||||
unsigned int dev_id;
|
||||
camsys_regulator_t avdd;
|
||||
camsys_regulator_t dovdd;
|
||||
camsys_regulator_t dvdd;
|
||||
camsys_regulator_t afvdd;
|
||||
camsys_gpio_t pwrdn;
|
||||
camsys_gpio_t rst;
|
||||
camsys_gpio_t afpwr;
|
||||
camsys_gpio_t afpwrdn;
|
||||
camsys_gpio_t pwren;
|
||||
camsys_flash_t fl;
|
||||
camsys_extdev_phy_t phy;
|
||||
camsys_extdev_clk_t clk;
|
||||
unsigned int dev_cfg;
|
||||
struct platform_device *pdev;
|
||||
struct list_head list;
|
||||
struct list_head active;
|
||||
} camsys_extdev_t;
|
||||
|
||||
typedef struct camsys_phyinfo_s {
|
||||
unsigned int phycnt;
|
||||
void *clk;
|
||||
camsys_meminfo_t *reg;
|
||||
int (*clkin_cb)(void *ptr, unsigned int on);
|
||||
int (*ops)(void *ptr, camsys_mipiphy_t *phy);
|
||||
int (*remove)(struct platform_device *pdev);
|
||||
} camsys_phyinfo_t;
|
||||
|
||||
typedef struct camsys_exdevs_s {
|
||||
struct mutex mut;
|
||||
struct list_head list;
|
||||
struct list_head active;
|
||||
} camsys_exdevs_t;
|
||||
|
||||
typedef struct camsys_dma_buf_s {
|
||||
struct dma_buf *dma_buf;
|
||||
struct dma_buf_attachment *attach;
|
||||
struct sg_table *sgt;
|
||||
dma_addr_t dma_addr;
|
||||
int fd;
|
||||
} camsys_dma_buf_t;
|
||||
|
||||
typedef struct camsys_dev_s {
|
||||
unsigned int dev_id;
|
||||
camsys_irq_t irq;
|
||||
camsys_devmems_t devmems;
|
||||
struct miscdevice miscdev;
|
||||
void *clk;
|
||||
camsys_phyinfo_t *mipiphy;
|
||||
camsys_phyinfo_t cifphy;
|
||||
|
||||
camsys_exdevs_t extdevs;
|
||||
struct list_head list;
|
||||
struct platform_device *pdev;
|
||||
|
||||
void *soc;
|
||||
|
||||
camsys_meminfo_t *csiphy_reg;
|
||||
camsys_meminfo_t *dsiphy_reg;
|
||||
camsys_meminfo_t *isp0_reg;
|
||||
|
||||
unsigned long rk_grf_base;
|
||||
unsigned long rk_cru_base;
|
||||
unsigned long rk_isp_base;
|
||||
atomic_t refcount;
|
||||
struct iommu_domain *domain;
|
||||
camsys_dma_buf_t dma_buf[CAMSYS_DMA_BUF_MAX_NUM];
|
||||
int dma_buf_cnt;
|
||||
|
||||
int (*clkin_cb)(void *ptr, unsigned int on);
|
||||
int (*clkout_cb)(void *ptr, unsigned int on, unsigned int clk);
|
||||
int (*reset_cb)(void *ptr, unsigned int on);
|
||||
|
||||
int (*phy_cb)
|
||||
(camsys_extdev_t *extdev,
|
||||
camsys_sysctrl_t *devctl, void *ptr);
|
||||
int (*iomux)(camsys_extdev_t *extdev, void *ptr);
|
||||
int (*platform_remove)(struct platform_device *pdev);
|
||||
int (*flash_trigger_cb)(void *ptr, int mode, unsigned int on);
|
||||
int (*iommu_cb)(void *ptr, camsys_sysctrl_t *devctl);
|
||||
} camsys_dev_t;
|
||||
|
||||
|
||||
static inline camsys_extdev_t *camsys_find_extdev(
|
||||
unsigned int dev_id, camsys_dev_t *camsys_dev)
|
||||
{
|
||||
camsys_extdev_t *extdev = NULL;
|
||||
|
||||
if (!list_empty(&camsys_dev->extdevs.list)) {
|
||||
list_for_each_entry(extdev,
|
||||
&camsys_dev->extdevs.list, list) {
|
||||
if (extdev->dev_id == dev_id) {
|
||||
return extdev;
|
||||
}
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline camsys_meminfo_t *camsys_find_devmem(
|
||||
char *name, camsys_dev_t *camsys_dev)
|
||||
{
|
||||
camsys_meminfo_t *devmem;
|
||||
|
||||
if (!list_empty(&camsys_dev->devmems.memslist)) {
|
||||
list_for_each_entry(devmem,
|
||||
&camsys_dev->devmems.memslist, list) {
|
||||
if (strcmp(devmem->name, name) == 0) {
|
||||
return devmem;
|
||||
}
|
||||
}
|
||||
}
|
||||
camsys_err("%s memory have not been find in %s!",
|
||||
name, dev_name(camsys_dev->miscdev.this_device));
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int camsys_sysctl_extdev(
|
||||
camsys_extdev_t *extdev, camsys_sysctrl_t *devctl, camsys_dev_t *camsys_dev)
|
||||
{
|
||||
int err = 0;
|
||||
camsys_regulator_t *regulator;
|
||||
camsys_gpio_t *gpio;
|
||||
|
||||
if ((devctl->ops > CamSys_Vdd_Start_Tag) &&
|
||||
(devctl->ops < CamSys_Vdd_End_Tag)) {
|
||||
regulator = &extdev->avdd;
|
||||
regulator += devctl->ops-1;
|
||||
|
||||
if (!IS_ERR_OR_NULL(regulator->ldo)) {
|
||||
if (devctl->on) {
|
||||
err = regulator_set_voltage(
|
||||
regulator->ldo, regulator->min_uv,
|
||||
regulator->max_uv);
|
||||
err |= regulator_enable(regulator->ldo);
|
||||
camsys_trace(1,
|
||||
"Sysctl %d success, regulator set (%d,%d) uv!",
|
||||
devctl->ops, regulator->min_uv,
|
||||
regulator->max_uv);
|
||||
} else {
|
||||
while (regulator_is_enabled(regulator->ldo) > 0)
|
||||
regulator_disable(regulator->ldo);
|
||||
camsys_trace(1,
|
||||
"Sysctl %d success, regulator off!",
|
||||
devctl->ops);
|
||||
}
|
||||
} else {
|
||||
err = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
} else if ((devctl->ops > CamSys_Gpio_Start_Tag) &&
|
||||
(devctl->ops < CamSys_Gpio_End_Tag)) {
|
||||
gpio = &extdev->pwrdn;
|
||||
gpio += devctl->ops - CamSys_Gpio_Start_Tag -1;
|
||||
|
||||
if (gpio->io != 0xffffffff) {
|
||||
if (devctl->on) {
|
||||
gpio_direction_output(gpio->io, gpio->active);
|
||||
gpio_set_value(gpio->io, gpio->active);
|
||||
camsys_trace(1,
|
||||
"Sysctl %d success, gpio(%d) set %d",
|
||||
devctl->ops, gpio->io, gpio->active);
|
||||
} else {
|
||||
gpio_direction_output(gpio->io, !gpio->active);
|
||||
gpio_set_value(gpio->io, !gpio->active);
|
||||
camsys_trace(1,
|
||||
"Sysctl %d success, gpio(%d) set %d",
|
||||
devctl->ops, gpio->io, !gpio->active);
|
||||
}
|
||||
} else {
|
||||
camsys_trace(1, "Sysctl %d not do, because gpio is NULL",
|
||||
devctl->ops);
|
||||
err = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
} else if (devctl->ops == CamSys_ClkIn) {
|
||||
if (camsys_dev->clkout_cb)
|
||||
camsys_dev->clkout_cb
|
||||
(camsys_dev, devctl->on,
|
||||
extdev->clk.in_rate);
|
||||
} else if (devctl->ops == CamSys_Phy) {
|
||||
if (camsys_dev->phy_cb)
|
||||
(camsys_dev->phy_cb)
|
||||
(extdev, devctl,
|
||||
(void *)camsys_dev);
|
||||
}
|
||||
|
||||
end:
|
||||
return err;
|
||||
}
|
||||
|
||||
extern struct file_operations camsys_fops;
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,85 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __CAMSYS_MARVIN_H__
|
||||
#define __CAMSYS_MARVIN_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
#define CAMSYS_MARVIN_IRQNAME "MarvinIrq"
|
||||
|
||||
#define MIS_V_START BIT(6)
|
||||
|
||||
#define MRV_ISP_BASE 0x400
|
||||
#define MRV_ISP_RIS (MRV_ISP_BASE + 0x1c0)
|
||||
#define MRV_ISP_MIS (MRV_ISP_BASE + 0x1c4)
|
||||
#define MRV_ISP_ICR (MRV_ISP_BASE + 0x1c8)
|
||||
|
||||
#define MRV_MIPI_BASE 0x1C00
|
||||
#define MRV_MIPI_MIS (MRV_MIPI_BASE + 0x10)
|
||||
#define MRV_MIPI_ICR (MRV_MIPI_BASE + 0x14)
|
||||
#define MRV_MIPI_FRAME (MRV_MIPI_BASE + 0x40)
|
||||
|
||||
#define MRV_MI_BASE (0x1400)
|
||||
|
||||
#define MRV_MI_MP_Y_OFFS_CNT_START (MRV_MI_BASE + 0x14)
|
||||
#define MRV_MI_INIT (MRV_MI_BASE + 0x4)
|
||||
#define MRV_MI_MP_Y_BASE_AD (MRV_MI_BASE + 0x8)
|
||||
#define MRV_MI_Y_BASE_AD_SHD (MRV_MI_BASE + 0x78)
|
||||
#define MRV_MI_Y_OFFS_CNT_SHD (MRV_MI_BASE + 0x80)
|
||||
#define MRV_MI_IMIS (MRV_MI_BASE + 0xf8)
|
||||
#define MRV_MI_RIS (MRV_MI_BASE + 0xfc)
|
||||
#define MRV_MI_MIS (MRV_MI_BASE + 0x100)
|
||||
#define MRV_MI_ICR (MRV_MI_BASE + 0x104)
|
||||
|
||||
#define MRV_FLASH_CONFIG (0x664)
|
||||
|
||||
#define MRV_JPG_BASE (0x1800)
|
||||
#define MRV_JPG_ERR_RIS (MRV_JPG_BASE + 0x6C)
|
||||
#define MRV_JPG_ERR_MIS (MRV_JPG_BASE + 0x70)
|
||||
#define MRV_JPG_ERR_ICR (MRV_JPG_BASE + 0x74)
|
||||
#define MRV_JPG_MIS (MRV_JPG_BASE + 0x84)
|
||||
#define MRV_JPG_RIS (MRV_JPG_BASE + 0x80)
|
||||
#define MRV_JPG_ICR (MRV_JPG_BASE + 0x88)
|
||||
|
||||
typedef enum IO_USE_TYPE_e {
|
||||
USE_AS_GPIO,
|
||||
USE_AS_ISP_INTERNAL,
|
||||
} IO_USE_TYPE_t;
|
||||
|
||||
typedef struct camsys_mrv_clk_s {
|
||||
struct clk *pd_isp;
|
||||
struct clk *hclk_isp;
|
||||
struct clk *aclk_isp;
|
||||
struct clk *isp;
|
||||
struct clk *isp_jpe;
|
||||
struct clk *pclkin_isp;
|
||||
struct clk *clk_mipi_24m;
|
||||
struct clk *clk_vio0_noc;
|
||||
bool in_on;
|
||||
|
||||
struct clk *cif_clk_out;
|
||||
struct clk *cif_clk_pll;
|
||||
struct clk *pclk_dphyrx;
|
||||
|
||||
unsigned int out_on;
|
||||
|
||||
struct clk *hclk_isp0_noc;
|
||||
struct clk *hclk_isp0_wrapper;
|
||||
struct clk *hclk_isp1_noc;
|
||||
struct clk *hclk_isp1_wrapper;
|
||||
struct clk *aclk_isp0_noc;
|
||||
struct clk *aclk_isp0_wrapper;
|
||||
struct clk *aclk_isp1_noc;
|
||||
struct clk *aclk_isp1_wrapper;
|
||||
struct clk *clk_isp0;
|
||||
struct clk *clk_isp1;
|
||||
struct clk *pclkin_isp1;
|
||||
struct clk *pclk_dphy_ref;
|
||||
struct clk *pclk_dphytxrx;
|
||||
|
||||
struct mutex lock;
|
||||
} camsys_mrv_clk_t;
|
||||
|
||||
int camsys_mrv_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,293 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#include "camsys_soc_priv.h"
|
||||
#include "camsys_mipicsi_phy.h"
|
||||
|
||||
unsigned int CHIP_TYPE;
|
||||
unsigned long rk_grf_base;
|
||||
unsigned long rk_cru_base;
|
||||
unsigned long rk_isp_base;
|
||||
|
||||
static int camsys_mipiphy_clkin_cb(void *ptr, unsigned int on)
|
||||
{
|
||||
camsys_mipiphy_clk_t *clk;
|
||||
camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
|
||||
unsigned int i, phycnt;
|
||||
|
||||
if (camsys_dev->mipiphy != NULL) {
|
||||
phycnt = camsys_dev->mipiphy[0].phycnt;
|
||||
|
||||
for (i = 0; i < phycnt; i++) {
|
||||
if (camsys_dev->mipiphy[i].clk != NULL) {
|
||||
clk = (camsys_mipiphy_clk_t *)
|
||||
camsys_dev->mipiphy[i].clk;
|
||||
if (on && !clk->on) {
|
||||
if (!IS_ERR_OR_NULL(clk->hclk))
|
||||
clk_prepare_enable(clk->hclk);
|
||||
clk->on = on;
|
||||
} else if (!on && clk->on) {
|
||||
if (!IS_ERR_OR_NULL(clk->hclk))
|
||||
clk_disable_unprepare
|
||||
(clk->hclk);
|
||||
clk->on = on;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (on)
|
||||
camsys_trace(2, "%s mipiphy clk turn on",
|
||||
dev_name(camsys_dev->miscdev.this_device));
|
||||
else
|
||||
camsys_trace(2, "%s mipiphy clk turn off",
|
||||
dev_name(camsys_dev->miscdev.this_device));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_mipiphy_ops(void *ptr, camsys_mipiphy_t *phy)
|
||||
{
|
||||
camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
|
||||
camsys_mipiphy_soc_para_t para;
|
||||
camsys_soc_priv_t *soc;
|
||||
|
||||
if (camsys_dev->soc) {
|
||||
soc = (camsys_soc_priv_t *)camsys_dev->soc;
|
||||
if (soc->soc_cfg) {
|
||||
para.camsys_dev = camsys_dev;
|
||||
para.phy = phy;
|
||||
(soc->soc_cfg)(camsys_dev, Mipi_Phy_Cfg, (void *)¶);
|
||||
} else {
|
||||
camsys_err("camsys_dev->soc->soc_cfg is NULL!");
|
||||
}
|
||||
} else {
|
||||
camsys_err("camsys_dev->soc is NULL!");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_mipiphy_remove_cb(struct platform_device *pdev)
|
||||
{
|
||||
camsys_dev_t *camsys_dev = platform_get_drvdata(pdev);
|
||||
camsys_mipiphy_clk_t *phyclk;
|
||||
unsigned int i = 0;
|
||||
unsigned long vir_base = camsys_dev->mipiphy[i].reg->vir_base;
|
||||
|
||||
if (camsys_dev->mipiphy != NULL) {
|
||||
for (i = 0; i < camsys_dev->mipiphy[0].phycnt; i++) {
|
||||
if (camsys_dev->mipiphy[i].reg != NULL) {
|
||||
if (camsys_dev->mipiphy[i].reg->vir_base != 0) {
|
||||
iounmap((void __iomem *)vir_base);
|
||||
vir_base = 0;
|
||||
}
|
||||
kfree(camsys_dev->mipiphy[i].reg);
|
||||
camsys_dev->mipiphy[i].reg = NULL;
|
||||
}
|
||||
|
||||
if (camsys_dev->mipiphy[i].clk != NULL) {
|
||||
phyclk =
|
||||
(camsys_mipiphy_clk_t *)
|
||||
camsys_dev->mipiphy[i].clk;
|
||||
devm_clk_put(&pdev->dev, phyclk->hclk);
|
||||
|
||||
kfree(camsys_dev->mipiphy[i].clk);
|
||||
camsys_dev->mipiphy[i].clk = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 ||
|
||||
CHIP_TYPE == 3399 || CHIP_TYPE == 3326) {
|
||||
if (camsys_dev->csiphy_reg != NULL) {
|
||||
kfree(camsys_dev->csiphy_reg);
|
||||
camsys_dev->csiphy_reg = NULL;
|
||||
}
|
||||
|
||||
if (camsys_dev->dsiphy_reg != NULL) {
|
||||
kfree(camsys_dev->dsiphy_reg);
|
||||
camsys_dev->dsiphy_reg = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int camsys_mipiphy_probe_cb(
|
||||
struct platform_device *pdev, camsys_dev_t *camsys_dev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
camsys_meminfo_t *meminfo;
|
||||
camsys_phyinfo_t *mipiphy;
|
||||
unsigned int mipiphy_cnt, phyreg[2];
|
||||
char str[31];
|
||||
struct clk *clk;
|
||||
camsys_mipiphy_clk_t *phyclk;
|
||||
int err, i;
|
||||
struct device_node *node;
|
||||
|
||||
err = of_property_read_u32(dev->of_node,
|
||||
"rockchip,isp,mipiphy", &mipiphy_cnt);
|
||||
if (err < 0) {
|
||||
camsys_err("get property(rockchip,isp,mipiphy) failed!");
|
||||
goto fail;
|
||||
} else {
|
||||
camsys_trace(2, "%s have %d mipi phy\n",
|
||||
dev_name(&pdev->dev), mipiphy_cnt);
|
||||
}
|
||||
|
||||
mipiphy = kzalloc(sizeof(camsys_phyinfo_t)*mipiphy_cnt, GFP_KERNEL);
|
||||
if (mipiphy == NULL) {
|
||||
err = -ENOMEM;
|
||||
camsys_err("malloc camsys_phyinfo_t failed!");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
camsys_dev->mipiphy = mipiphy;
|
||||
|
||||
memset(str, 0x00, sizeof(str));
|
||||
for (i = 0; i < mipiphy_cnt; i++) {
|
||||
meminfo = NULL;
|
||||
sprintf(str, "rockchip,isp,mipiphy%d,reg", i);
|
||||
if (of_property_read_u32_array(
|
||||
dev->of_node, str, phyreg, 2
|
||||
) == 0
|
||||
) {
|
||||
meminfo = kzalloc(sizeof(camsys_meminfo_t), GFP_KERNEL);
|
||||
if (meminfo == NULL) {
|
||||
camsys_err(
|
||||
"malloc camsys_meminfo_t for mipiphy%d failed!",
|
||||
i);
|
||||
} else {
|
||||
meminfo->vir_base =
|
||||
(unsigned long)
|
||||
ioremap(phyreg[0], phyreg[1]);
|
||||
if (!meminfo->vir_base) {
|
||||
camsys_err("%s ioremap %s failed",
|
||||
dev_name(&pdev->dev), str);
|
||||
} else {
|
||||
strlcpy(meminfo->name,
|
||||
CAMSYS_MIPIPHY_MEM_NAME,
|
||||
sizeof(meminfo->name));
|
||||
meminfo->phy_base = phyreg[0];
|
||||
meminfo->size = phyreg[1];
|
||||
}
|
||||
camsys_dev->mipiphy[i].reg = meminfo;
|
||||
}
|
||||
}
|
||||
|
||||
sprintf(str, "hclk_mipiphy%d", i);
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, str);
|
||||
if (!IS_ERR_OR_NULL(clk)) {
|
||||
phyclk =
|
||||
kzalloc(sizeof(camsys_mipiphy_clk_t),
|
||||
GFP_KERNEL);
|
||||
if (phyclk == NULL) {
|
||||
camsys_err("malloc camsys_mipiphy_clk_t for %s failed!",
|
||||
str);
|
||||
} else {
|
||||
phyclk->hclk = clk;
|
||||
}
|
||||
|
||||
camsys_dev->mipiphy[i].clk = (void *)phyclk;
|
||||
}
|
||||
|
||||
camsys_dev->mipiphy[i].phycnt = mipiphy_cnt;
|
||||
camsys_dev->mipiphy[i].clkin_cb = camsys_mipiphy_clkin_cb;
|
||||
camsys_dev->mipiphy[i].ops = camsys_mipiphy_ops;
|
||||
camsys_dev->mipiphy[i].remove = camsys_mipiphy_remove_cb;
|
||||
|
||||
if (meminfo != NULL) {
|
||||
camsys_trace(1, "%s mipi phy%d probe success "
|
||||
"(reg_phy: 0x%lx reg_vir: 0x%lx size: 0x%x)\n",
|
||||
dev_name(&pdev->dev), i, meminfo->phy_base,
|
||||
meminfo->vir_base, meminfo->size);
|
||||
} else {
|
||||
camsys_trace(1, "%s mipi phy%d probe success "
|
||||
"(reg_phy: 0x%x reg_vir: 0x%x size: 0x%x)\n",
|
||||
dev_name(&pdev->dev), i, 0, 0, 0);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 ||
|
||||
CHIP_TYPE == 3399 || CHIP_TYPE == 3288 || CHIP_TYPE == 3326) {
|
||||
|
||||
if (CHIP_TYPE == 3399) {
|
||||
camsys_dev->dsiphy_reg =
|
||||
kzalloc(sizeof(camsys_meminfo_t), GFP_KERNEL);
|
||||
if (camsys_dev->dsiphy_reg == NULL) {
|
||||
camsys_err("malloc camsys_meminfo_t for dsiphy_reg failed!");
|
||||
err = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (of_property_read_u32_array(
|
||||
dev->of_node,
|
||||
"rockchip,isp,dsiphy,reg", phyreg, 2
|
||||
) == 0
|
||||
) {
|
||||
camsys_dev->dsiphy_reg->vir_base =
|
||||
(unsigned long)
|
||||
ioremap(phyreg[0], phyreg[1]);
|
||||
if (!camsys_dev->dsiphy_reg->vir_base) {
|
||||
camsys_err("%s ioremap %s failed",
|
||||
dev_name(&pdev->dev),
|
||||
"rockchip,isp,dsiphy,reg");
|
||||
} else {
|
||||
strlcpy(camsys_dev->dsiphy_reg->name,
|
||||
"Dsi-DPHY",
|
||||
sizeof(camsys_dev->dsiphy_reg->name));
|
||||
camsys_dev->dsiphy_reg->phy_base = phyreg[0];
|
||||
camsys_dev->dsiphy_reg->size = phyreg[1];
|
||||
}
|
||||
}
|
||||
|
||||
} else {
|
||||
camsys_dev->csiphy_reg =
|
||||
kzalloc(sizeof(camsys_meminfo_t), GFP_KERNEL);
|
||||
if (camsys_dev->csiphy_reg == NULL) {
|
||||
camsys_err("malloc camsys_meminfo_t for csiphy_reg failed!");
|
||||
err = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (of_property_read_u32_array(
|
||||
dev->of_node,
|
||||
"rockchip,isp,csiphy,reg", phyreg, 2
|
||||
) == 0
|
||||
) {
|
||||
camsys_dev->csiphy_reg->vir_base =
|
||||
(unsigned long)
|
||||
ioremap(phyreg[0], phyreg[1]);
|
||||
if (!camsys_dev->csiphy_reg->vir_base) {
|
||||
camsys_err("%s ioremap %s failed",
|
||||
dev_name(&pdev->dev),
|
||||
"rockchip,isp,csiphy,reg");
|
||||
} else {
|
||||
strlcpy(camsys_dev->csiphy_reg->name,
|
||||
"Csi-DPHY",
|
||||
sizeof(camsys_dev->csiphy_reg->name));
|
||||
camsys_dev->csiphy_reg->phy_base =
|
||||
phyreg[0];
|
||||
camsys_dev->csiphy_reg->size =
|
||||
phyreg[1];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* get cru base */
|
||||
node = of_parse_phandle(dev->of_node, "rockchip,cru", 0);
|
||||
camsys_dev->rk_cru_base = (unsigned long)of_iomap(node, 0);
|
||||
camsys_trace(2, "rk_cru_base=0x%lx", camsys_dev->rk_cru_base);
|
||||
/* get grf base */
|
||||
node = of_parse_phandle(dev->of_node, "rockchip,grf", 0);
|
||||
camsys_dev->rk_grf_base = (unsigned long)of_iomap(node, 0);
|
||||
camsys_trace(2, "rk_grf_base=0x%lx", camsys_dev->rk_grf_base);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
@@ -1,15 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __CAMSYS_MIPICSI_PHY_H__
|
||||
#define __CAMSYS_MIPICSI_PHY_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
typedef struct camsys_mipiphy_clk_s {
|
||||
struct clk *hclk;
|
||||
|
||||
unsigned int on;
|
||||
} camsys_mipiphy_clk_t;
|
||||
|
||||
int camsys_mipiphy_probe_cb
|
||||
(struct platform_device *pdev, camsys_dev_t *camsys_dev);
|
||||
#endif
|
||||
@@ -1,80 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#include "camsys_soc_priv.h"
|
||||
|
||||
|
||||
static camsys_soc_priv_t *camsys_soc_p;
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
extern int camsys_rk3368_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
|
||||
extern int camsys_rk3366_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
|
||||
extern int camsys_rk3399_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
|
||||
extern int camsys_rk3326_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
|
||||
#else
|
||||
extern int camsys_rk3288_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para);
|
||||
#endif
|
||||
camsys_soc_priv_t *camsys_soc_get(void)
|
||||
{
|
||||
if (camsys_soc_p != NULL) {
|
||||
return camsys_soc_p;
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
int camsys_soc_init(unsigned int chip_type)
|
||||
{
|
||||
camsys_soc_p = kzalloc(sizeof(camsys_soc_priv_t), GFP_KERNEL);
|
||||
if (camsys_soc_p == NULL) {
|
||||
camsys_err("malloc camsys_soc_priv_t failed!");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
if (chip_type == 3368) {
|
||||
strlcpy(camsys_soc_p->name, "camsys_rk3368", 31);
|
||||
camsys_soc_p->soc_cfg = camsys_rk3368_cfg;
|
||||
camsys_trace(2, "rk3368 exit!");
|
||||
} else if (chip_type == 3366) {
|
||||
strlcpy(camsys_soc_p->name, "camsys_rk3366", 31);
|
||||
camsys_soc_p->soc_cfg = camsys_rk3366_cfg;
|
||||
camsys_trace(2, "rk3366 exit!");
|
||||
} else if (chip_type == 3399) {
|
||||
strlcpy(camsys_soc_p->name, "camsys_rk3399", 31);
|
||||
camsys_soc_p->soc_cfg = camsys_rk3399_cfg;
|
||||
camsys_trace(2, "rk3399 exit!");
|
||||
} else if (chip_type == 3326) {
|
||||
strlcpy(camsys_soc_p->name, "camsys_rk3326", 31);
|
||||
camsys_soc_p->soc_cfg = camsys_rk3326_cfg;
|
||||
camsys_trace(2, "rk3326 exit!");
|
||||
}
|
||||
#else
|
||||
if (chip_type == 3288) {
|
||||
strlcpy(camsys_soc_p->name, "camsys_rk3288", 31);
|
||||
camsys_soc_p->soc_cfg = camsys_rk3288_cfg;
|
||||
camsys_trace(2, "rk3288 exit!");
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
if (camsys_soc_p != NULL) {
|
||||
kfree(camsys_soc_p);
|
||||
camsys_soc_p = NULL;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int camsys_soc_deinit(void)
|
||||
{
|
||||
if (camsys_soc_p != NULL) {
|
||||
kfree(camsys_soc_p);
|
||||
camsys_soc_p = NULL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@@ -1,41 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RKCAMSYS_SOC_PRIV_H__
|
||||
#define __RKCAMSYS_SOC_PRIV_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
typedef struct camsys_mipiphy_soc_para_s {
|
||||
camsys_dev_t *camsys_dev;
|
||||
camsys_mipiphy_t *phy;
|
||||
} camsys_mipiphy_soc_para_t;
|
||||
|
||||
typedef enum camsys_soc_cfg_e {
|
||||
Clk_DriverStrength_Cfg = 0,
|
||||
Cif_IoDomain_Cfg,
|
||||
Mipi_Phy_Cfg,
|
||||
|
||||
Isp_SoftRst,
|
||||
} camsys_soc_cfg_t;
|
||||
|
||||
typedef struct camsys_soc_priv_s {
|
||||
char name[32];
|
||||
|
||||
int (*soc_cfg)
|
||||
(camsys_dev_t *camsys_dev,
|
||||
camsys_soc_cfg_t cfg_cmd,
|
||||
void *cfg_para
|
||||
);
|
||||
|
||||
} camsys_soc_priv_t;
|
||||
|
||||
extern camsys_soc_priv_t *camsys_soc_get(void);
|
||||
extern int camsys_soc_init(unsigned int);
|
||||
extern int camsys_soc_deinit(void);
|
||||
|
||||
extern unsigned long rk_grf_base;
|
||||
extern unsigned long rk_cru_base;
|
||||
extern unsigned long rk_isp_base;
|
||||
extern unsigned int CHIP_TYPE;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,404 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifdef CONFIG_ARM
|
||||
#include "camsys_soc_priv.h"
|
||||
#include "camsys_soc_rk3288.h"
|
||||
|
||||
struct mipiphy_hsfreqrange_s {
|
||||
unsigned int range_l;
|
||||
unsigned int range_h;
|
||||
unsigned char cfg_bit;
|
||||
};
|
||||
|
||||
static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
|
||||
{80, 90, 0x00},
|
||||
{90, 100, 0x10},
|
||||
{100, 110, 0x20},
|
||||
{110, 130, 0x01},
|
||||
{130, 140, 0x11},
|
||||
{140, 150, 0x21},
|
||||
{150, 170, 0x02},
|
||||
{170, 180, 0x12},
|
||||
{180, 200, 0x22},
|
||||
{200, 220, 0x03},
|
||||
{220, 240, 0x13},
|
||||
{240, 250, 0x23},
|
||||
{250, 270, 0x4},
|
||||
{270, 300, 0x14},
|
||||
{300, 330, 0x5},
|
||||
{330, 360, 0x15},
|
||||
{360, 400, 0x25},
|
||||
{400, 450, 0x06},
|
||||
{450, 500, 0x16},
|
||||
{500, 550, 0x07},
|
||||
{550, 600, 0x17},
|
||||
{600, 650, 0x08},
|
||||
{650, 700, 0x18},
|
||||
{700, 750, 0x09},
|
||||
{750, 800, 0x19},
|
||||
{800, 850, 0x29},
|
||||
{850, 900, 0x39},
|
||||
{900, 950, 0x0a},
|
||||
{950, 1000, 0x1a}
|
||||
|
||||
};
|
||||
|
||||
static int camsys_rk3288_mipiphy0_wr_reg(
|
||||
unsigned char addr, unsigned char data, camsys_mipiphy_soc_para_t *para)
|
||||
{
|
||||
/* TESTCLK=1 */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
|
||||
/* TESTEN =1,TESTDIN=addr */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
((addr << DPHY_RX0_TESTDIN_OFFSET)
|
||||
| DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN |
|
||||
DPHY_RX0_TESTEN_MASK));
|
||||
/* TESTCLK=0 */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX0_TESTCLK_MASK);
|
||||
|
||||
if (data != 0xff) { /* write data ? */
|
||||
/* TESTEN =0,TESTDIN=data */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
((data << DPHY_RX0_TESTDIN_OFFSET)
|
||||
| DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
|
||||
|
||||
/* TESTCLK=1 */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX0_TESTCLK_MASK |
|
||||
DPHY_RX0_TESTCLK);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int camsys_rk3288_mipiphy0_rd_reg(unsigned char addr)
|
||||
{
|
||||
return read_grf_reg(GRF_SOC_STATUS21);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int camsys_rk3288_mipiphy1_wr_reg(
|
||||
unsigned int phy_virt, unsigned char addr, unsigned char data)
|
||||
{
|
||||
/* TESTEN =1,TESTDIN=addr */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
|
||||
/* TESTCLK=0 */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
|
||||
/* TESTEN =0,TESTDIN=data */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
|
||||
/* TESTCLK=1 */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_rk3288_mipiphy1_rd_reg(
|
||||
unsigned int phy_virt, unsigned char addr)
|
||||
{
|
||||
return (read_csihost_reg
|
||||
(((CSIHOST_PHY_TEST_CTRL1) & 0xff00)) >> 8);
|
||||
}
|
||||
|
||||
static int camsys_rk3288_mipihpy_cfg(
|
||||
camsys_mipiphy_soc_para_t *para)
|
||||
{
|
||||
unsigned char hsfreqrange = 0xff, i;
|
||||
struct mipiphy_hsfreqrange_s *hsfreqrange_p;
|
||||
unsigned int phy_virt, phy_index;
|
||||
unsigned int *base;
|
||||
unsigned int data_en_bit, data_en_num = 0;
|
||||
|
||||
phy_index = para->phy->phy_index;
|
||||
if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
|
||||
phy_virt =
|
||||
para->camsys_dev->mipiphy[phy_index].reg->vir_base;
|
||||
} else {
|
||||
phy_virt = 0x00;
|
||||
}
|
||||
|
||||
if ((para->phy->bit_rate == 0) ||
|
||||
(para->phy->data_en_bit == 0)) {
|
||||
if (para->phy->phy_index == 0) {
|
||||
base =
|
||||
(unsigned int *)
|
||||
para->camsys_dev->devmems.registermem->vir_base;
|
||||
*(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL) / 4)
|
||||
&= ~(0x0f << 8);
|
||||
camsys_trace(1, "mipi phy 0 standby!");
|
||||
} else if (para->phy->phy_index == 1) {
|
||||
/* SHUTDOWNZ=0 */
|
||||
write_csihost_reg
|
||||
(CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
|
||||
/* RSTZ=0 */
|
||||
write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
|
||||
|
||||
camsys_trace(1, "mipi phy 1 standby!");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
hsfreqrange_p = mipiphy_hsfreqrange;
|
||||
for (i = 0;
|
||||
i <
|
||||
(sizeof(mipiphy_hsfreqrange) /
|
||||
sizeof(struct mipiphy_hsfreqrange_s));
|
||||
i++) {
|
||||
if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
|
||||
(para->phy->bit_rate <= hsfreqrange_p->range_h)) {
|
||||
hsfreqrange = hsfreqrange_p->cfg_bit;
|
||||
break;
|
||||
}
|
||||
hsfreqrange_p++;
|
||||
}
|
||||
|
||||
if (hsfreqrange == 0xff) {
|
||||
camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
|
||||
para->phy->bit_rate);
|
||||
hsfreqrange = 0x00;
|
||||
}
|
||||
hsfreqrange <<= 1;
|
||||
|
||||
if (para->phy->phy_index == 0) {
|
||||
write_grf_reg(GRF_SOC_CON6_OFFSET,
|
||||
MIPI_PHY_DPHYSEL_OFFSET_MASK
|
||||
| (para->phy->phy_index
|
||||
<< MIPI_PHY_DPHYSEL_OFFSET_BIT));
|
||||
|
||||
/* set lane num */
|
||||
write_grf_reg(GRF_SOC_CON10_OFFSET,
|
||||
DPHY_RX0_ENABLE_MASK
|
||||
| (para->phy->data_en_bit
|
||||
<< DPHY_RX0_ENABLE_OFFSET_BITS));
|
||||
/* set lan turndisab as 1 */
|
||||
write_grf_reg(GRF_SOC_CON10_OFFSET,
|
||||
DPHY_RX0_TURN_DISABLE_MASK
|
||||
| (0xf
|
||||
<< DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
|
||||
write_grf_reg(GRF_SOC_CON10_OFFSET,
|
||||
(0x0 << 4) | (0xf << 20));
|
||||
/* set lan turnrequest as 0 */
|
||||
write_grf_reg(GRF_SOC_CON15_OFFSET,
|
||||
DPHY_RX0_TURN_REQUEST_MASK
|
||||
| (0x0
|
||||
<< DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
|
||||
|
||||
/* phy start */
|
||||
{
|
||||
/* TESTCLK=1 */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX0_TESTCLK_MASK
|
||||
| DPHY_RX0_TESTCLK);
|
||||
/* TESTCLR=1 */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX0_TESTCLR_MASK
|
||||
| DPHY_RX0_TESTCLR);
|
||||
udelay(100);
|
||||
/* TESTCLR=0 zyc */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX0_TESTCLR_MASK);
|
||||
udelay(100);
|
||||
|
||||
/* set clock lane */
|
||||
camsys_rk3288_mipiphy0_wr_reg
|
||||
(0x34, 0x15, para);
|
||||
if (para->phy->data_en_bit >= 0x00)
|
||||
camsys_rk3288_mipiphy0_wr_reg
|
||||
(0x44, hsfreqrange, para);
|
||||
if (para->phy->data_en_bit >= 0x01)
|
||||
camsys_rk3288_mipiphy0_wr_reg(
|
||||
0x54, hsfreqrange, para);
|
||||
if (para->phy->data_en_bit >= 0x04) {
|
||||
camsys_rk3288_mipiphy0_wr_reg
|
||||
(0x84, hsfreqrange, para);
|
||||
camsys_rk3288_mipiphy0_wr_reg
|
||||
(0x94, hsfreqrange, para);
|
||||
}
|
||||
|
||||
/* Normal operation */
|
||||
camsys_rk3288_mipiphy0_wr_reg(0x0, -1, para);
|
||||
/* TESTCLK=1 */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX0_TESTCLK_MASK
|
||||
| DPHY_RX0_TESTCLK);
|
||||
/* TESTEN =0 */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
(DPHY_RX0_TESTEN_MASK));
|
||||
}
|
||||
|
||||
base =
|
||||
(unsigned int *)
|
||||
para->camsys_dev->devmems.registermem->vir_base;
|
||||
*(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL) / 4)
|
||||
|= (0x0f << 8);
|
||||
|
||||
} else if (para->phy->phy_index == 1) {
|
||||
/* 7. Set BASEDIR_N to the desired values. */
|
||||
/* Real IC route must set firstly */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_TX1RX1_BASEDIR_REC
|
||||
| DPHY_TX1RX1_BASEDIR_OFFSET);
|
||||
/* 1'b1: MIPI PHY TX1RX1 1'b0: MIPI PHY RX0 */
|
||||
write_grf_reg(GRF_SOC_CON6_OFFSET,
|
||||
MIPI_PHY_DPHYSEL_OFFSET_MASK
|
||||
| (para->phy->phy_index
|
||||
<< MIPI_PHY_DPHYSEL_OFFSET_BIT));
|
||||
/* 1'b1: CSI host 1'b0: DSI host1 */
|
||||
write_grf_reg(GRF_SOC_CON6_OFFSET,
|
||||
DSI_CSI_TESTBUS_SEL_MASK
|
||||
| (1
|
||||
<< DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
|
||||
/* 1'b1: isp 1'b0: csi host */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_RX1_SRC_SEL_CSI
|
||||
| DPHY_RX1_SRC_SEL_MASK);
|
||||
/* 1.Set RSTZ = 1'b0 */
|
||||
write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
|
||||
/* 2. Set SHUTDOWNZ = 1'b0. */
|
||||
write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
|
||||
/* 3. Set TESTCLEAR = 1'b1. */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000001);
|
||||
/* 4.Apply REFCLK signal with the appropriate frequency; */
|
||||
/* 5. Apply CFG_CLK signal with the appropriate frequency; */
|
||||
/* 6. Set MASTERSLAVEZ = 1'b1 (for MASTER) / 1'b0 (for SLAVE). */
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_TX1RX1_SLAVEZ
|
||||
| DPHY_TX1RX1_MASTERSLAVEZ_MASK);
|
||||
/* 8. Set all REQUEST inputs to zero. */
|
||||
write_grf_reg(GRF_SOC_CON15_OFFSET,
|
||||
DPHY_TX1RX1_TURN_REQUEST_MASK
|
||||
| (0x0
|
||||
<< DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
|
||||
/* MIPI DPHY TX1RX1 disable turn around control */
|
||||
write_grf_reg(GRF_SOC_CON9_OFFSET,
|
||||
DPHY_TX1RX1_TURN_DISABLE_MASK
|
||||
| (0xf
|
||||
<< DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
|
||||
/* MIPI DPHY TX1RX1 force lane into receive mode */
|
||||
/* wait for stop sta */
|
||||
write_grf_reg(GRF_SOC_CON9_OFFSET,
|
||||
(DPHY_TX1RX1_FORCE_RX_MODE_OFFSET_BITS
|
||||
<< 4)
|
||||
| DPHY_TX1RX1_FORCE_RX_MODE_MASK);
|
||||
/* 9. Wait for 15 ns. */
|
||||
udelay(1);
|
||||
/* 10. Set TESTCLR to low. */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
/* 11. Wait for 15 ns. */
|
||||
udelay(1);
|
||||
camsys_rk3288_mipiphy1_wr_reg(phy_virt, 0x34, 0x15);
|
||||
/* 12. Configure Test Code 0x44 hsfreqrange. */
|
||||
camsys_rk3288_mipiphy1_wr_reg(phy_virt, 0x44, hsfreqrange);
|
||||
camsys_rk3288_mipiphy1_rd_reg(phy_virt, 0x0);
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, 0x00000000);
|
||||
/* 15.Set ENABLE_N=1'b1. */
|
||||
data_en_bit = para->phy->data_en_bit;
|
||||
data_en_bit = data_en_bit >> 1;
|
||||
data_en_num = 0;
|
||||
while (data_en_bit) {
|
||||
data_en_num++;
|
||||
data_en_bit = data_en_bit >> 1;
|
||||
}
|
||||
write_csihost_reg(CSIHOST_N_LANES, data_en_num);
|
||||
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
||||
DPHY_TX1RX1_ENABLECLK
|
||||
| DPHY_TX1RX1_ENABLECLK_MASK);
|
||||
/* 16. Wait for 5 ns. */
|
||||
udelay(1);
|
||||
/* 17. Set SHUTDOWNZ = 1'b1. */
|
||||
write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000001);
|
||||
/* 18. Wait for 5 ns. */
|
||||
udelay(1);
|
||||
/* 19.Set RSTZ = 1'b1 */
|
||||
write_csihost_reg
|
||||
(CSIHOST_DPHY_RSTZ, 0x00000001);
|
||||
} else {
|
||||
camsys_err("mipi phy index %d is invalidate!",
|
||||
para->phy->phy_index);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",
|
||||
para->phy->phy_index,
|
||||
para->phy->data_en_bit,
|
||||
para->phy->bit_rate);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define MRV_AFM_BASE 0x0000
|
||||
#define VI_IRCL 0x0014
|
||||
|
||||
int camsys_rk3288_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
|
||||
{
|
||||
unsigned int *para_int;
|
||||
|
||||
switch (cfg_cmd) {
|
||||
case Clk_DriverStrength_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
__raw_writel((((*para_int) & 0x03) << 3)|(0x03 << 3),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x01d4));
|
||||
break;
|
||||
}
|
||||
|
||||
case Cif_IoDomain_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
if (*para_int < 28000000) {
|
||||
/* 1.8v IO */
|
||||
__raw_writel
|
||||
(((1 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0380));
|
||||
} else {
|
||||
/* 3.3v IO */
|
||||
__raw_writel
|
||||
(((0 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0380));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Mipi_Phy_Cfg: {
|
||||
camsys_mipiphy_soc_para_t *para
|
||||
= (camsys_mipiphy_soc_para_t *)cfg_para;
|
||||
|
||||
if (para->phy->dir == CamSys_Mipiphy_Tx &&
|
||||
para->phy->phy_index == 1) {
|
||||
/* TX1/RX1 DPHY switch to RX status */
|
||||
__raw_writel(0xa000a000,
|
||||
(void *)(camsys_dev->rk_grf_base + 0x027c));
|
||||
} else {
|
||||
camsys_rk3288_mipihpy_cfg
|
||||
((camsys_mipiphy_soc_para_t *)cfg_para);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Isp_SoftRst: { /* ddl@rock-chips.com: v0.d.0 */
|
||||
unsigned int reset;
|
||||
|
||||
reset = (unsigned int)cfg_para;
|
||||
if (reset == 1)
|
||||
__raw_writel(0x80, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
else
|
||||
__raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
camsys_trace(2, "Isp self soft rst: %d", reset);
|
||||
break;
|
||||
}
|
||||
|
||||
default: {
|
||||
camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ARM */
|
||||
@@ -1,130 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RKCAMSYS_SOC_RK3288_H__
|
||||
#define __RKCAMSYS_SOC_RK3288_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
/*MARVIN REGISTER*/
|
||||
#define MRV_MIPI_BASE 0x1C00
|
||||
#define MRV_MIPI_CTRL 0x00
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON14
|
||||
*bit 0 dphy_rx0_testclr
|
||||
*bit 1 dphy_rx0_testclk
|
||||
*bit 2 dphy_rx0_testen
|
||||
*bit 3:10 dphy_rx0_testdin
|
||||
*/
|
||||
#define GRF_SOC_CON14_OFFSET (0x027c)
|
||||
#define DPHY_RX0_TESTCLR_MASK (0x1 << 16)
|
||||
#define DPHY_RX0_TESTCLK_MASK (0x1 << 17)
|
||||
#define DPHY_RX0_TESTEN_MASK (0x1 << 18)
|
||||
#define DPHY_RX0_TESTDIN_MASK (0xff << 19)
|
||||
|
||||
#define DPHY_RX0_TESTCLR (0x1 << 0)
|
||||
#define DPHY_RX0_TESTCLK (0x1 << 1)
|
||||
#define DPHY_RX0_TESTEN (0x1 << 2)
|
||||
#define DPHY_RX0_TESTDIN_OFFSET (3)
|
||||
|
||||
#define DPHY_TX1RX1_ENABLECLK_MASK (0x1 << 28)
|
||||
#define DPHY_RX1_SRC_SEL_MASK (0x1 << 29)
|
||||
#define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 30)
|
||||
#define DPHY_TX1RX1_BASEDIR_OFFSET (0x1 << 31)
|
||||
|
||||
#define DPHY_TX1RX1_ENABLECLK (0x1 << 12)
|
||||
#define DPHY_TX1RX1_DISABLECLK (0x0 << 12)
|
||||
#define DPHY_RX1_SRC_SEL_ISP (0x1 << 13)
|
||||
#define DPHY_RX1_SRC_SEL_CSI (0x0 << 13)
|
||||
#define DPHY_TX1RX1_SLAVEZ (0x0 << 14)
|
||||
#define DPHY_TX1RX1_BASEDIR_REC (0x1 << 15)
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON6
|
||||
*bit 0 grf_con_disable_isp
|
||||
*bit 1 grf_con_isp_dphy_sel 1'b0 mipi phy rx0
|
||||
*/
|
||||
#define GRF_SOC_CON6_OFFSET (0x025c)
|
||||
#define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
|
||||
#define MIPI_PHY_DISABLE_ISP (0x0 << 0)
|
||||
|
||||
#define DSI_CSI_TESTBUS_SEL_MASK (0x1 << 30)
|
||||
#define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
|
||||
|
||||
#define MIPI_PHY_DPHYSEL_OFFSET_MASK (0x1 << 17)
|
||||
#define MIPI_PHY_DPHYSEL_OFFSET_BIT (0x1)
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON10
|
||||
*bit12:15 grf_dphy_rx0_enable
|
||||
*bit 0:3 turn disable
|
||||
*/
|
||||
#define GRF_SOC_CON10_OFFSET (0x026c)
|
||||
#define DPHY_RX0_TURN_DISABLE_MASK (0xf << 16)
|
||||
#define DPHY_RX0_TURN_DISABLE_OFFSET_BITS (0x0)
|
||||
#define DPHY_RX0_ENABLE_MASK (0xf << 28)
|
||||
#define DPHY_RX0_ENABLE_OFFSET_BITS (12)
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON9
|
||||
*bit12:15 grf_dphy_rx0_enable
|
||||
*bit 0:3 turn disable
|
||||
*/
|
||||
#define GRF_SOC_CON9_OFFSET (0x0268)
|
||||
#define DPHY_TX1RX1_TURN_DISABLE_MASK (0xf << 16)
|
||||
#define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0)
|
||||
#define DPHY_TX1RX1_ENABLE_MASK (0xf << 28)
|
||||
#define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12)
|
||||
#define DPHY_TX1RX1_FORCE_RX_MODE_MASK (0xf << 20)
|
||||
#define DPHY_TX1RX1_FORCE_RX_MODE_OFFSET_BITS (0x0)
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON15
|
||||
*bit 0:3 turn request
|
||||
*/
|
||||
#define GRF_SOC_CON15_OFFSET (0x03a4)
|
||||
#define DPHY_RX0_TURN_REQUEST_MASK (0xf << 16)
|
||||
#define DPHY_RX0_TURN_REQUEST_OFFSET_BITS (0x0)
|
||||
|
||||
#define DPHY_TX1RX1_TURN_REQUEST_MASK (0xf << 20)
|
||||
#define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS (0x0)
|
||||
|
||||
#define GRF_SOC_STATUS21 (0x2D4)
|
||||
|
||||
#define CSIHOST_PHY_TEST_CTRL0 (0x30)
|
||||
#define CSIHOST_PHY_TEST_CTRL1 (0x34)
|
||||
#define CSIHOST_PHY_SHUTDOWNZ (0x08)
|
||||
#define CSIHOST_DPHY_RSTZ (0x0c)
|
||||
#define CSIHOST_N_LANES (0x04)
|
||||
#define CSIHOST_CSI2_RESETN (0x10)
|
||||
#define CSIHOST_PHY_STATE (0x14)
|
||||
#define CSIHOST_DATA_IDS1 (0x18)
|
||||
#define CSIHOST_DATA_IDS2 (0x1C)
|
||||
#define CSIHOST_ERR1 (0x20)
|
||||
#define CSIHOST_ERR2 (0x24)
|
||||
|
||||
#define write_grf_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define read_grf_reg(addr) \
|
||||
__raw_readl((void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define mask_grf_reg(addr, msk, val) \
|
||||
write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
|
||||
#ifdef CONFIG_ARM64
|
||||
#define cru_writel(v, o) \
|
||||
do {writel(v, RK_CRU_VIRT + (o)); } \
|
||||
while (0)
|
||||
|
||||
#define write_csihost_reg(addr, val) \
|
||||
__raw_writel(val, addr + (void __force __iomem *)(phy_virt))
|
||||
#define read_csihost_reg(addr) \
|
||||
__raw_readl(addr + (void __force __iomem *)(phy_virt))
|
||||
#else
|
||||
#define cru_writel(v, o) \
|
||||
do {writel(v, RK_CRU_VIRT + (o)); dsb(); } \
|
||||
while (0)
|
||||
|
||||
#define write_csihost_reg(addr, val) \
|
||||
__raw_writel(val, addr + IOMEM(phy_virt))
|
||||
#define read_csihost_reg(addr) \
|
||||
__raw_readl(addr + IOMEM(phy_virt))
|
||||
#endif
|
||||
#endif
|
||||
@@ -1,239 +0,0 @@
|
||||
/*
|
||||
*************************************************************************
|
||||
* Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
#include "camsys_soc_priv.h"
|
||||
#include "camsys_soc_rk3326.h"
|
||||
#include "camsys_marvin.h"
|
||||
|
||||
struct mipiphy_hsfreqrange_s {
|
||||
unsigned int range_l;
|
||||
unsigned int range_h;
|
||||
unsigned char cfg_bit;
|
||||
};
|
||||
|
||||
static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
|
||||
{80, 110, 0x00},
|
||||
{110, 150, 0x01},
|
||||
{150, 200, 0x02},
|
||||
{200, 250, 0x03},
|
||||
{250, 300, 0x04},
|
||||
{300, 400, 0x05},
|
||||
{400, 500, 0x06},
|
||||
{500, 600, 0x07},
|
||||
{600, 700, 0x08},
|
||||
{700, 800, 0x09},
|
||||
{800, 1000, 0xa},
|
||||
{1000, 1100, 0xb},
|
||||
{1100, 1250, 0xc},
|
||||
{1250, 1350, 0xd},
|
||||
{1350, 1500, 0xe}
|
||||
};
|
||||
|
||||
static int camsys_rk3326_mipihpy_cfg(camsys_mipiphy_soc_para_t *para)
|
||||
{
|
||||
unsigned char hsfreqrange = 0xff, i;
|
||||
struct mipiphy_hsfreqrange_s *hsfreqrange_p;
|
||||
unsigned long csiphy_virt;
|
||||
//unsigned long base;
|
||||
|
||||
if (para->camsys_dev->csiphy_reg) {
|
||||
csiphy_virt =
|
||||
(unsigned long)para->camsys_dev->csiphy_reg->vir_base;
|
||||
} else {
|
||||
csiphy_virt = 0x00;
|
||||
}
|
||||
if (para->phy->bit_rate == 0 ||
|
||||
para->phy->data_en_bit == 0) {
|
||||
if (para->phy->phy_index == 0) {
|
||||
write_grf_reg(GRF_PD_VI_CON_OFFSET,
|
||||
DPHY_CSIPHY_CLKLANE_EN_OFFSET_MASK |
|
||||
(0 << DPHY_CSIPHY_CLKLANE_EN_OFFSET_BITS));
|
||||
write_grf_reg(GRF_PD_VI_CON_OFFSET,
|
||||
DPHY_CSIPHY_DATALANE_EN_OFFSET_MASK |
|
||||
(0 << DPHY_CSIPHY_DATALANE_EN_OFFSET_BITS));
|
||||
camsys_trace(1, "mipi phy 0 standby!");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
hsfreqrange_p = mipiphy_hsfreqrange;
|
||||
for (i = 0;
|
||||
i < (sizeof(mipiphy_hsfreqrange) /
|
||||
sizeof(struct mipiphy_hsfreqrange_s));
|
||||
i++) {
|
||||
if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
|
||||
(para->phy->bit_rate <= hsfreqrange_p->range_h)) {
|
||||
hsfreqrange = hsfreqrange_p->cfg_bit;
|
||||
break;
|
||||
}
|
||||
hsfreqrange_p++;
|
||||
}
|
||||
|
||||
if (hsfreqrange == 0xff) {
|
||||
camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
|
||||
para->phy->bit_rate);
|
||||
hsfreqrange = 0x00;
|
||||
}
|
||||
|
||||
if (para->phy->phy_index == 0) {
|
||||
/* phy start */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
|
||||
|
||||
/* set data lane num and enable clock lane */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET,
|
||||
((para->phy->data_en_bit << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
|
||||
(0x1 << MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT) | 0x1));
|
||||
/* Reset dphy analog part */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
|
||||
usleep_range(500, 1000);
|
||||
/* Reset dphy digital part */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
|
||||
/* not into receive mode/wait stopstate */
|
||||
write_grf_reg(GRF_PD_VI_CON_OFFSET,
|
||||
DPHY_CSIPHY_FORCERXMODE_OFFSET_MASK |
|
||||
(0x0 << DPHY_CSIPHY_FORCERXMODE_OFFSET_BITS));
|
||||
|
||||
write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100),
|
||||
hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x100) & (~0xf)));
|
||||
|
||||
if (para->phy->data_en_bit > 0x00) {
|
||||
write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x180), hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x180) & (~0xf)));
|
||||
}
|
||||
if (para->phy->data_en_bit > 0x02) {
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x200, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x200) & (~0xf)));
|
||||
}
|
||||
if (para->phy->data_en_bit > 0x04) {
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x280, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x280) & (~0xf)));
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x300, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x300) & (~0xf)));
|
||||
}
|
||||
|
||||
write_grf_reg(GRF_PD_VI_CON_OFFSET,
|
||||
DPHY_CSIPHY_CLKLANE_EN_OFFSET_MASK |
|
||||
(1 << DPHY_CSIPHY_CLKLANE_EN_OFFSET_BITS));
|
||||
write_grf_reg(GRF_PD_VI_CON_OFFSET,
|
||||
DPHY_CSIPHY_DATALANE_EN_OFFSET_MASK |
|
||||
(0x0f << DPHY_CSIPHY_DATALANE_EN_OFFSET_BITS));
|
||||
|
||||
} else {
|
||||
camsys_err("mipi phy index %d is invalidate!",
|
||||
para->phy->phy_index);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",
|
||||
para->phy->phy_index,
|
||||
para->phy->data_en_bit, para->phy->bit_rate);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define VI_IRCL 0x0014
|
||||
/**
|
||||
* reset on too high isp_clk rate will result in bus dead.
|
||||
* The signoff isp_clk rate is 350M, and the recommended rate
|
||||
* on reset from IC is NOT greater than 300M.
|
||||
*/
|
||||
#define SAFETY_RESET_ISPCLK_RATE_LIMIT 300000000
|
||||
int camsys_rk3326_cfg
|
||||
(
|
||||
camsys_dev_t *camsys_dev,
|
||||
camsys_soc_cfg_t cfg_cmd,
|
||||
void *cfg_para
|
||||
)
|
||||
{
|
||||
unsigned int *para_int;
|
||||
|
||||
switch (cfg_cmd) {
|
||||
case Clk_DriverStrength_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
__raw_writel((((*para_int) & 0x03) << 6) | (0x03 << 22),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x104));//m0 cifclk_out
|
||||
break;
|
||||
}
|
||||
|
||||
case Cif_IoDomain_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
if (*para_int < 28000000) {
|
||||
/* 1.8v IO */
|
||||
__raw_writel((1 << GRF_IO_VSEL_VCCIO3_BITS) | GRF_IO_VSEL_VCCIO3_MASK,
|
||||
(void *)(camsys_dev->rk_grf_base + GRF_IO_VSEL_OFFSET));
|
||||
} else {
|
||||
/* 3.3v IO */
|
||||
__raw_writel((0 << GRF_IO_VSEL_VCCIO3_BITS) | GRF_IO_VSEL_VCCIO3_MASK,
|
||||
(void *)(camsys_dev->rk_grf_base + GRF_IO_VSEL_OFFSET));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Mipi_Phy_Cfg: {
|
||||
camsys_rk3326_mipihpy_cfg
|
||||
((camsys_mipiphy_soc_para_t *)cfg_para);
|
||||
break;
|
||||
}
|
||||
|
||||
case Isp_SoftRst: {/* ddl@rock-chips.com: v0.d.0 */
|
||||
unsigned long reset;
|
||||
|
||||
reset = (unsigned long)cfg_para;
|
||||
|
||||
if (reset == 1) {
|
||||
camsys_mrv_clk_t *clk =
|
||||
(camsys_mrv_clk_t *)camsys_dev->clk;
|
||||
long old_ispclk_rate = clk_get_rate(clk->isp);
|
||||
|
||||
/* check the isp_clk before isp reset operation */
|
||||
if (old_ispclk_rate > SAFETY_RESET_ISPCLK_RATE_LIMIT)
|
||||
clk_set_rate(clk->isp,
|
||||
SAFETY_RESET_ISPCLK_RATE_LIMIT);
|
||||
__raw_writel(0x80, (void *)(camsys_dev->rk_isp_base +
|
||||
VI_IRCL));
|
||||
usleep_range(100, 200);
|
||||
__raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
|
||||
VI_IRCL));
|
||||
/* restore the old ispclk after reset */
|
||||
if (old_ispclk_rate != SAFETY_RESET_ISPCLK_RATE_LIMIT)
|
||||
clk_set_rate(clk->isp, old_ispclk_rate);
|
||||
}
|
||||
camsys_trace(2, "Isp self soft rst: %ld", reset);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ARM64 */
|
||||
@@ -1,77 +0,0 @@
|
||||
/*
|
||||
*************************************************************************
|
||||
* Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __RKCAMSYS_SOC_RK3326_H__
|
||||
#define __RKCAMSYS_SOC_RK3326_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
/* MARVIN REGISTER */
|
||||
#define MRV_MIPI_BASE 0x1C00
|
||||
#define MRV_MIPI_CTRL 0x00
|
||||
|
||||
#define GRF_IO_VSEL_OFFSET (0x0180)
|
||||
#define GRF_IO_VSEL_VCCIO3_MASK (0x1 << 20)
|
||||
#define GRF_IO_VSEL_VCCIO3_BITS (4)
|
||||
#define GRF_PD_VI_CON_OFFSET (0x0430)
|
||||
/* bit 13-14 */
|
||||
#define ISP_CIF_IF_DATAWIDTH_MASK (0x3 << 29)
|
||||
#define ISP_CIF_IF_DATAWIDTH_8B (0x0 << 13)
|
||||
#define ISP_CIF_IF_DATAWIDTH_10B (0x1 << 13)
|
||||
#define ISP_CIF_IF_DATAWIDTH_12B (0x2 << 13)
|
||||
|
||||
/* bit 9 */
|
||||
#define DPHY_CSIPHY_CLK_INV_SEL_MASK (0x1 << 25)
|
||||
#define DPHY_CSIPHY_CLK_INV_SEL (0x1 << 9)
|
||||
/* bit 8 */
|
||||
#define DPHY_CSIPHY_CLKLANE_EN_OFFSET_MASK (0x1 << 24)//????
|
||||
#define DPHY_CSIPHY_CLKLANE_EN_OFFSET_BITS (8)
|
||||
/* bit 4-7 */
|
||||
#define DPHY_CSIPHY_DATALANE_EN_OFFSET_MASK (0xF << 20)//?????
|
||||
#define DPHY_CSIPHY_DATALANE_EN_OFFSET_BITS (4)
|
||||
/* bit 0-3 */
|
||||
#define DPHY_CSIPHY_FORCERXMODE_OFFSET_MASK (0xF << 16)
|
||||
#define DPHY_CSIPHY_FORCERXMODE_OFFSET_BITS (0)
|
||||
|
||||
/* LOW POWER MODE SET */
|
||||
/* base */
|
||||
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET (0x00)
|
||||
#define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT (2)
|
||||
#define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT (6)
|
||||
#define MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET (0x04)
|
||||
#define MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET (0x80)
|
||||
#define MIPI_CSI_DPHY_CTRL_SIG_INV_OFFSET (0x84)
|
||||
|
||||
/* Configure the count time of the THS-SETTLE by protocol. */
|
||||
#define MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET (0x00)
|
||||
/* MSB enable for pin_rxdatahs_
|
||||
* 1: enable
|
||||
* 0: disable
|
||||
*/
|
||||
#define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38)
|
||||
|
||||
#define write_grf_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define read_grf_reg(addr) \
|
||||
__raw_readl((void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define mask_grf_reg(addr, msk, val) \
|
||||
write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
|
||||
|
||||
#define write_cru_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_cru_base))
|
||||
/* csi phy */
|
||||
#define write_csiphy_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + csiphy_virt))
|
||||
#define read_csiphy_reg(addr) \
|
||||
__raw_readl((void *)(addr + csiphy_virt))
|
||||
|
||||
#endif
|
||||
@@ -1,257 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifdef CONFIG_ARM64
|
||||
#include "camsys_soc_priv.h"
|
||||
#include "camsys_soc_rk3366.h"
|
||||
|
||||
struct mipiphy_hsfreqrange_s {
|
||||
unsigned int range_l;
|
||||
unsigned int range_h;
|
||||
unsigned char cfg_bit;
|
||||
};
|
||||
|
||||
static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
|
||||
{80, 110, 0x00},
|
||||
{110, 150, 0x01},
|
||||
{150, 200, 0x02},
|
||||
{200, 250, 0x03},
|
||||
{250, 300, 0x04},
|
||||
{300, 400, 0x05},
|
||||
{400, 500, 0x06},
|
||||
{500, 600, 0x07},
|
||||
{600, 700, 0x08},
|
||||
{700, 800, 0x09},
|
||||
{800, 1000, 0xa},
|
||||
{1000, 1100, 0xb},
|
||||
{1100, 1250, 0xc},
|
||||
{1250, 1350, 0xd},
|
||||
{1350, 1500, 0xe}
|
||||
};
|
||||
|
||||
#if 0
|
||||
static int camsys_rk3368_mipiphy_wr_reg(
|
||||
unsigned long phy_virt, unsigned char addr, unsigned char data)
|
||||
{
|
||||
/*TESTEN =1,TESTDIN=addr */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
|
||||
/*TESTCLK=0 */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
|
||||
udelay(10);
|
||||
/*TESTEN =0,TESTDIN=data */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
|
||||
/*TESTCLK=1 */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_rk3368_mipiphy_rd_reg(
|
||||
unsigned long phy_virt, unsigned char addr)
|
||||
{
|
||||
return (read_csihost_reg(((CSIHOST_PHY_TEST_CTRL1) & 0xff00))>>8);
|
||||
}
|
||||
|
||||
static int camsys_rk3368_csiphy_wr_reg(
|
||||
unsigned long csiphy_virt, unsigned char addr, unsigned char data)
|
||||
{
|
||||
write_csiphy_reg(addr, data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_rk3368_csiphy_rd_reg(
|
||||
unsigned long csiphy_virt, unsigned char addr)
|
||||
{
|
||||
return read_csiphy_reg(addr);
|
||||
}
|
||||
#endif
|
||||
static int camsys_rk3366_mipihpy_cfg(
|
||||
camsys_mipiphy_soc_para_t *para)
|
||||
{
|
||||
unsigned char hsfreqrange = 0xff, i;
|
||||
struct mipiphy_hsfreqrange_s *hsfreqrange_p;
|
||||
unsigned long phy_virt, phy_index;
|
||||
unsigned long base;
|
||||
unsigned long csiphy_virt;
|
||||
|
||||
phy_index = para->phy->phy_index;
|
||||
if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
|
||||
phy_virt = para->camsys_dev->mipiphy[phy_index].reg->vir_base;
|
||||
} else {
|
||||
phy_virt = 0x00;
|
||||
}
|
||||
if (para->camsys_dev->csiphy_reg != NULL) {
|
||||
csiphy_virt =
|
||||
(unsigned long)para->camsys_dev->csiphy_reg->vir_base;
|
||||
} else {
|
||||
csiphy_virt = 0x00;
|
||||
}
|
||||
if ((para->phy->bit_rate == 0) ||
|
||||
(para->phy->data_en_bit == 0)) {
|
||||
if (para->phy->phy_index == 0) {
|
||||
base =
|
||||
(unsigned long)
|
||||
para->camsys_dev->devmems.registermem->vir_base;
|
||||
*((unsigned int *)
|
||||
(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
|
||||
&= ~(0x0f << 8);
|
||||
camsys_trace(1, "mipi phy 0 standby!");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
hsfreqrange_p = mipiphy_hsfreqrange;
|
||||
for (i = 0;
|
||||
i <
|
||||
(sizeof(mipiphy_hsfreqrange)/
|
||||
sizeof(struct mipiphy_hsfreqrange_s));
|
||||
i++) {
|
||||
|
||||
if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
|
||||
(para->phy->bit_rate <= hsfreqrange_p->range_h)) {
|
||||
hsfreqrange = hsfreqrange_p->cfg_bit;
|
||||
break;
|
||||
}
|
||||
hsfreqrange_p++;
|
||||
}
|
||||
|
||||
if (hsfreqrange == 0xff) {
|
||||
camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
|
||||
para->phy->bit_rate);
|
||||
hsfreqrange = 0x00;
|
||||
}
|
||||
|
||||
if (para->phy->phy_index == 0) {
|
||||
/* isp select */
|
||||
/*write_grf_reg
|
||||
(GRF_SOC_CON6_OFFSET, ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK
|
||||
| (1 << ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT));
|
||||
*/
|
||||
/* phy start */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
|
||||
|
||||
/* set data lane num and enable clock lane */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET,
|
||||
((para->phy->data_en_bit << 2) | (0x1 << 6) | 0x1));
|
||||
/* Reset dphy analog part */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
|
||||
usleep_range(500, 1000);
|
||||
/* Reset dphy digital part */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
|
||||
|
||||
write_grf_reg(GRF_SOC_CON6_OFFSET,
|
||||
MIPI_CSI_DPHY_RX_FORCERXMODE_MASK |
|
||||
MIPI_CSI_DPHY_RX_FORCERXMODE_BIT);
|
||||
|
||||
write_csiphy_reg
|
||||
((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100),
|
||||
hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x100) & (~0xf)));
|
||||
|
||||
if (para->phy->data_en_bit > 0x00) {
|
||||
write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x180), hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x180) & (~0xf)));
|
||||
}
|
||||
if (para->phy->data_en_bit > 0x02) {
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x200, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x200) & (~0xf)));
|
||||
}
|
||||
if (para->phy->data_en_bit > 0x04) {
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x280, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x280) & (~0xf)));
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x300, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x300) & (~0xf)));
|
||||
}
|
||||
/*
|
||||
* MIPI CTRL bit8:11 SHUTDOWN_LANE are invert
|
||||
* connect to dphy pin_enable_x
|
||||
*/
|
||||
base =
|
||||
(unsigned long)
|
||||
para->camsys_dev->devmems.registermem->vir_base;
|
||||
*((unsigned int *)(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
|
||||
&= ~(0x0f << 8);
|
||||
} else {
|
||||
camsys_err("mipi phy index %d is invalidate!",
|
||||
para->phy->phy_index);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",
|
||||
para->phy->phy_index, para->phy->data_en_bit, para->phy->bit_rate);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define MRV_AFM_BASE 0x0000
|
||||
#define VI_IRCL 0x0014
|
||||
int camsys_rk3366_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
|
||||
{
|
||||
unsigned int *para_int;
|
||||
|
||||
switch (cfg_cmd) {
|
||||
case Clk_DriverStrength_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
__raw_writel((((*para_int) & 0x03) << 3) | (0x03 << 3),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x204));
|
||||
/* set 0xffffffff to max all */
|
||||
break;
|
||||
}
|
||||
|
||||
case Cif_IoDomain_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
if (*para_int < 28000000) {
|
||||
/* 1.8v IO */
|
||||
__raw_writel(((1 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0900));
|
||||
} else {
|
||||
/* 3.3v IO */
|
||||
__raw_writel(((0 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0900));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Mipi_Phy_Cfg: {
|
||||
camsys_rk3366_mipihpy_cfg
|
||||
((camsys_mipiphy_soc_para_t *)cfg_para);
|
||||
break;
|
||||
}
|
||||
|
||||
case Isp_SoftRst: /* ddl@rock-chips.com: v0.d.0 */ {
|
||||
unsigned long reset;
|
||||
reset = (unsigned long)cfg_para;
|
||||
if (reset == 1)
|
||||
__raw_writel(0x80, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
else
|
||||
__raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
camsys_trace(2, "Isp self soft rst: %ld", reset);
|
||||
break;
|
||||
}
|
||||
|
||||
default: {
|
||||
camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ARM64 */
|
||||
@@ -1,123 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RKCAMSYS_SOC_RK3366_H__
|
||||
#define __RKCAMSYS_SOC_RK3366_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
/*MARVIN REGISTER*/
|
||||
#define MRV_MIPI_BASE 0x1C00
|
||||
#define MRV_MIPI_CTRL 0x00
|
||||
|
||||
/*
|
||||
*#define CSIHOST_PHY_TEST_CTRL0_OFFSET 0x0030
|
||||
#define DPHY_TX1RX1_TESTCLR (1<<0)
|
||||
#define DPHY_TX1RX1_TESTCLK (1<<1)
|
||||
|
||||
#define CSIHOST_PHY_TEST_CTRL1_OFFSET 0x0034
|
||||
#define DPHY_TX1RX1_TESTDIN_OFFSET_BITS (0)
|
||||
#define DPHY_TX1RX1_TESTDOUT_OFFSET_BITS (8)
|
||||
#define DPHY_TX1RX1_TESTEN (16)
|
||||
*/
|
||||
|
||||
#define GRF_SOC_STATUS21 (0x2D4)
|
||||
|
||||
#define CSIHOST_PHY_TEST_CTRL0 (0x30)
|
||||
#define CSIHOST_PHY_TEST_CTRL1 (0x34)
|
||||
#define CSIHOST_N_LANES (0x04)
|
||||
#define CSIHOST_PHY_SHUTDOWNZ (0x08)
|
||||
#define CSIHOST_CSI2_RESETN (0x10)
|
||||
#define CSIHOST_DPHY_RSTZ (0x0c)
|
||||
#define CSIHOST_PHY_STATE (0x14)
|
||||
#define CSIHOST_DATA_IDS1 (0x18)
|
||||
#define CSIHOST_DATA_IDS2 (0x1C)
|
||||
#define CSIHOST_ERR1 (0x20)
|
||||
#define CSIHOST_ERR2 (0x24)
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON6
|
||||
*dphy_rx_forcerxmode 11:8
|
||||
*isp_mipi_csi_host_sel:1
|
||||
*disable_isp:0
|
||||
*bit 0 grf_con_disable_isp
|
||||
*bit 1 isp_mipi_csi_host_sel 1'b0: mipi csi host
|
||||
*/
|
||||
#define GRF_SOC_CON6_OFFSET (0x0418)
|
||||
/*bit 0*/
|
||||
#define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
|
||||
#define MIPI_PHY_DISABLE_ISP (0x0 << 0)
|
||||
/*bit 1*/
|
||||
#define ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK (0x1 << 17)
|
||||
#define ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT (0x1)
|
||||
/*bit 6*/
|
||||
#define DPHY_RX_CLK_INV_SEL_MASK (0x1 << 22)
|
||||
#define DPHY_RX_CLK_INV_SEL (0x1 << 6)
|
||||
/*bit 11:8*/
|
||||
#define DPHY_RX_FORCERXMODE_OFFSET_MASK (0xF << 24)
|
||||
#define DPHY_RX_FORCERXMODE_OFFSET_BITS (8)
|
||||
|
||||
/*GRF_SOC_CON7*/
|
||||
/*dphy_tx0_forcerxmode*/
|
||||
#define GRF_SOC_CON7_OFFSET (0x041c)
|
||||
/*bit 10:7*/
|
||||
#define FORCETXSTOPMODE_OFFSET_BITS (7)
|
||||
#define FORCETXSTOPMODE_MASK (0xF << 23)
|
||||
|
||||
#define DPHY_TX0_FORCERXMODE (6)
|
||||
#define DPHY_TX0_FORCERXMODE_MASK (0x01 << 22)
|
||||
/*bit 5*/
|
||||
#define LANE0_TURNDISABLE_BITS (5)
|
||||
#define LANE0_TURNDISABLE_MASK (0x01 << 21)
|
||||
|
||||
#define GRF_SOC_STATUS13 (0x04b4)
|
||||
/*dphy_rx_rxclkactivehs*/
|
||||
/*dphy_rx_direction*/
|
||||
/*dphy_rx_ulpsactivenot_0...3*/
|
||||
|
||||
/*LOW POWER MODE SET*/
|
||||
/*base*/
|
||||
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET (0x00)
|
||||
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET_BIT (2)
|
||||
|
||||
#define MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET (0x04)
|
||||
#define MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET (0x80)
|
||||
#define MIPI_CSI_DPHY_CTRL_SIG_INV_OFFSET (0x84)
|
||||
|
||||
/*Configure the count time of the THS-SETTLE by protocol.*/
|
||||
#define MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET (0x00)
|
||||
/*MSB enable for pin_rxdatahs_
|
||||
*1: enable
|
||||
*0: disable
|
||||
*/
|
||||
#define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38)
|
||||
|
||||
#define MIPI_CSI_DPHY_RX_FORCERXMODE_MASK (0x0f << 24)
|
||||
#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (0 << 8)
|
||||
|
||||
#define CSIHOST_N_LANES_OFFSET 0x04
|
||||
#define CSIHOST_N_LANES_OFFSET_BIT (0)
|
||||
|
||||
#define write_grf_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define read_grf_reg(addr) \
|
||||
__raw_readl((void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define mask_grf_reg(addr, msk, val) \
|
||||
write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
|
||||
|
||||
#define write_cru_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_cru_base))
|
||||
|
||||
/*#define cru_writel(v, o) do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
|
||||
* while (0)
|
||||
*/
|
||||
|
||||
#define write_csihost_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + phy_virt))
|
||||
#define read_csihost_reg(addr) \
|
||||
__raw_readl((void *)(addr + phy_virt))
|
||||
/*csi phy*/
|
||||
#define write_csiphy_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + csiphy_virt))
|
||||
#define read_csiphy_reg(addr) \
|
||||
__raw_readl((void *)(addr + csiphy_virt))
|
||||
|
||||
#endif
|
||||
@@ -1,257 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifdef CONFIG_ARM64
|
||||
#include "camsys_soc_priv.h"
|
||||
#include "camsys_soc_rk3368.h"
|
||||
|
||||
|
||||
struct mipiphy_hsfreqrange_s {
|
||||
unsigned int range_l;
|
||||
unsigned int range_h;
|
||||
unsigned char cfg_bit;
|
||||
};
|
||||
|
||||
static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
|
||||
{80, 110, 0x00},
|
||||
{110, 150, 0x01},
|
||||
{150, 200, 0x02},
|
||||
{200, 250, 0x03},
|
||||
{250, 300, 0x04},
|
||||
{300, 400, 0x05},
|
||||
{400, 500, 0x06},
|
||||
{500, 600, 0x07},
|
||||
{600, 700, 0x08},
|
||||
{700, 800, 0x09},
|
||||
{800, 1000, 0xa},
|
||||
{1000, 1100, 0xb},
|
||||
{1100, 1250, 0xc},
|
||||
{1250, 1350, 0xd},
|
||||
{1350, 1500, 0xe}
|
||||
};
|
||||
|
||||
#if 0
|
||||
static int camsys_rk3368_mipiphy_wr_reg
|
||||
(unsigned long phy_virt, unsigned char addr, unsigned char data)
|
||||
{
|
||||
/*TESTEN =1,TESTDIN=addr */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
|
||||
/*TESTCLK=0 */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
|
||||
udelay(10);
|
||||
/*TESTEN =0,TESTDIN=data */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
|
||||
/*TESTCLK=1 */
|
||||
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_rk3368_mipiphy_rd_reg
|
||||
(unsigned long phy_virt, unsigned char addr)
|
||||
{
|
||||
return (read_csihost_reg(((CSIHOST_PHY_TEST_CTRL1)&0xff00))>>8);
|
||||
}
|
||||
|
||||
static int camsys_rk3368_csiphy_wr_reg
|
||||
(unsigned long csiphy_virt, unsigned char addr, unsigned char data)
|
||||
{
|
||||
write_csiphy_reg(addr, data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_rk3368_csiphy_rd_reg
|
||||
(unsigned long csiphy_virt, unsigned char addr)
|
||||
{
|
||||
return read_csiphy_reg(addr);
|
||||
}
|
||||
#endif
|
||||
static int camsys_rk3368_mipihpy_cfg(camsys_mipiphy_soc_para_t *para)
|
||||
{
|
||||
unsigned char hsfreqrange = 0xff, i;
|
||||
struct mipiphy_hsfreqrange_s *hsfreqrange_p;
|
||||
unsigned long phy_virt, phy_index;
|
||||
unsigned long base;
|
||||
unsigned long csiphy_virt;
|
||||
|
||||
phy_index = para->phy->phy_index;
|
||||
if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
|
||||
phy_virt = para->camsys_dev->mipiphy[phy_index].reg->vir_base;
|
||||
} else {
|
||||
phy_virt = 0x00;
|
||||
}
|
||||
if (para->camsys_dev->csiphy_reg != NULL) {
|
||||
csiphy_virt =
|
||||
(unsigned long)para->camsys_dev->csiphy_reg->vir_base;
|
||||
} else {
|
||||
csiphy_virt = 0x00;
|
||||
}
|
||||
if ((para->phy->bit_rate == 0) ||
|
||||
(para->phy->data_en_bit == 0)) {
|
||||
if (para->phy->phy_index == 0) {
|
||||
base =
|
||||
(unsigned long)
|
||||
para->camsys_dev->devmems.registermem->vir_base;
|
||||
*((unsigned int *)
|
||||
(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
|
||||
&= ~(0x0f << 8);
|
||||
camsys_trace(1, "mipi phy 0 standby!");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
hsfreqrange_p = mipiphy_hsfreqrange;
|
||||
for (i = 0;
|
||||
i < (sizeof(mipiphy_hsfreqrange)/
|
||||
sizeof(struct mipiphy_hsfreqrange_s));
|
||||
i++) {
|
||||
|
||||
if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
|
||||
(para->phy->bit_rate <= hsfreqrange_p->range_h)) {
|
||||
hsfreqrange = hsfreqrange_p->cfg_bit;
|
||||
break;
|
||||
}
|
||||
hsfreqrange_p++;
|
||||
}
|
||||
|
||||
if (hsfreqrange == 0xff) {
|
||||
camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
|
||||
para->phy->bit_rate);
|
||||
hsfreqrange = 0x00;
|
||||
}
|
||||
|
||||
if (para->phy->phy_index == 0) {
|
||||
/* isp select */
|
||||
write_grf_reg(GRF_SOC_CON6_OFFSET, ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK
|
||||
| (1 << ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT));
|
||||
|
||||
/* phy start */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
|
||||
|
||||
/* set data lane num and enable clock lane */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET,
|
||||
((para->phy->data_en_bit << MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET_BIT) |
|
||||
(0x1 << 6) | 0x1));
|
||||
/* Reset dphy analog part */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
|
||||
usleep_range(500, 1000);
|
||||
/* Reset dphy digital part */
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
|
||||
|
||||
write_grf_reg(GRF_SOC_CON6_OFFSET,
|
||||
MIPI_CSI_DPHY_RX_FORCERXMODE_MASK |
|
||||
(0x0 << MIPI_CSI_DPHY_RX_FORCERXMODE_BIT));
|
||||
|
||||
write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100),
|
||||
hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x100) & (~0xf)));
|
||||
|
||||
if (para->phy->data_en_bit > 0x00) {
|
||||
write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x180), hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x180) & (~0xf)));
|
||||
}
|
||||
if (para->phy->data_en_bit > 0x02) {
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x200, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x200) & (~0xf)));
|
||||
}
|
||||
if (para->phy->data_en_bit > 0x04) {
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x280, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x280) & (~0xf)));
|
||||
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x300, hsfreqrange |
|
||||
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
|
||||
+ 0x300) & (~0xf)));
|
||||
}
|
||||
/*
|
||||
* MIPI CTRL bit8:11 SHUTDOWN_LANE are invert
|
||||
* connect to dphy pin_enable_x
|
||||
*/
|
||||
base = (unsigned long)para->camsys_dev->devmems.registermem->vir_base;
|
||||
*((unsigned int *)(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
|
||||
&= ~(0x0f << 8);
|
||||
} else {
|
||||
camsys_err("mipi phy index %d is invalidate!",
|
||||
para->phy->phy_index);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",
|
||||
para->phy->phy_index,
|
||||
para->phy->data_en_bit, para->phy->bit_rate);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define MRV_AFM_BASE 0x0000
|
||||
#define VI_IRCL 0x0014
|
||||
int camsys_rk3368_cfg(
|
||||
camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
|
||||
{
|
||||
unsigned int *para_int;
|
||||
|
||||
switch (cfg_cmd) {
|
||||
case Clk_DriverStrength_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
__raw_writel((((*para_int) & 0x03) << 3) | (0x03 << 3),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x204));
|
||||
/* set 0xffffffff to max all */
|
||||
break;
|
||||
}
|
||||
|
||||
case Cif_IoDomain_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
if (*para_int < 28000000) {
|
||||
/* 1.8v IO */
|
||||
__raw_writel(((1 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0900));
|
||||
} else {
|
||||
/* 3.3v IO */
|
||||
__raw_writel(((0 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0900));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Mipi_Phy_Cfg: {
|
||||
camsys_rk3368_mipihpy_cfg
|
||||
((camsys_mipiphy_soc_para_t *)cfg_para);
|
||||
break;
|
||||
}
|
||||
|
||||
case Isp_SoftRst: {/* ddl@rock-chips.com: v0.d.0 */
|
||||
unsigned long reset;
|
||||
|
||||
reset = (unsigned long)cfg_para;
|
||||
|
||||
if (reset == 1)
|
||||
__raw_writel(0x80, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
else
|
||||
__raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
camsys_trace(2, "Isp self soft rst: %ld", reset);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ARM64 */
|
||||
@@ -1,123 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RKCAMSYS_SOC_RK3368_H__
|
||||
#define __RKCAMSYS_SOC_RK3368_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
/*MARVIN REGISTER*/
|
||||
#define MRV_MIPI_BASE 0x1C00
|
||||
#define MRV_MIPI_CTRL 0x00
|
||||
|
||||
/*
|
||||
*#define CSIHOST_PHY_TEST_CTRL0_OFFSET 0x0030
|
||||
#define DPHY_TX1RX1_TESTCLR (1<<0)
|
||||
#define DPHY_TX1RX1_TESTCLK (1<<1)
|
||||
|
||||
#define CSIHOST_PHY_TEST_CTRL1_OFFSET 0x0034
|
||||
#define DPHY_TX1RX1_TESTDIN_OFFSET_BITS (0)
|
||||
#define DPHY_TX1RX1_TESTDOUT_OFFSET_BITS (8)
|
||||
#define DPHY_TX1RX1_TESTEN (16)
|
||||
*/
|
||||
|
||||
#define GRF_SOC_STATUS21 (0x2D4)
|
||||
|
||||
#define CSIHOST_PHY_TEST_CTRL0 (0x30)
|
||||
#define CSIHOST_PHY_TEST_CTRL1 (0x34)
|
||||
#define CSIHOST_N_LANES (0x04)
|
||||
#define CSIHOST_PHY_SHUTDOWNZ (0x08)
|
||||
#define CSIHOST_CSI2_RESETN (0x10)
|
||||
#define CSIHOST_DPHY_RSTZ (0x0c)
|
||||
#define CSIHOST_PHY_STATE (0x14)
|
||||
#define CSIHOST_DATA_IDS1 (0x18)
|
||||
#define CSIHOST_DATA_IDS2 (0x1C)
|
||||
#define CSIHOST_ERR1 (0x20)
|
||||
#define CSIHOST_ERR2 (0x24)
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON6
|
||||
*dphy_rx_forcerxmode 11:8
|
||||
*isp_mipi_csi_host_sel:1
|
||||
*disable_isp:0
|
||||
*bit 0 grf_con_disable_isp
|
||||
*bit 1 isp_mipi_csi_host_sel 1'b0: mipi csi host
|
||||
*/
|
||||
#define GRF_SOC_CON6_OFFSET (0x0418)
|
||||
/*bit 0*/
|
||||
#define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
|
||||
#define MIPI_PHY_DISABLE_ISP (0x0 << 0)
|
||||
/*bit 1*/
|
||||
#define ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK (0x1 << 17)
|
||||
#define ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT (0x1)
|
||||
/*bit 6*/
|
||||
#define DPHY_RX_CLK_INV_SEL_MASK (0x1 << 22)
|
||||
#define DPHY_RX_CLK_INV_SEL (0x1 << 6)
|
||||
/*bit 11:8*/
|
||||
#define DPHY_RX_FORCERXMODE_OFFSET_MASK (0xF << 24)
|
||||
#define DPHY_RX_FORCERXMODE_OFFSET_BITS (8)
|
||||
|
||||
/*GRF_SOC_CON7*/
|
||||
/*dphy_tx0_forcerxmode*/
|
||||
#define GRF_SOC_CON7_OFFSET (0x041c)
|
||||
/*bit 10:7*/
|
||||
#define FORCETXSTOPMODE_OFFSET_BITS (7)
|
||||
#define FORCETXSTOPMODE_MASK (0xF << 23)
|
||||
|
||||
#define DPHY_TX0_FORCERXMODE (6)
|
||||
#define DPHY_TX0_FORCERXMODE_MASK (0x01 << 22)
|
||||
/*bit 5*/
|
||||
#define LANE0_TURNDISABLE_BITS (5)
|
||||
#define LANE0_TURNDISABLE_MASK (0x01 << 21)
|
||||
|
||||
#define GRF_SOC_STATUS13 (0x04b4)
|
||||
/*dphy_rx_rxclkactivehs*/
|
||||
/*dphy_rx_direction*/
|
||||
/*dphy_rx_ulpsactivenot_0...3*/
|
||||
|
||||
/*LOW POWER MODE SET*/
|
||||
/*base*/
|
||||
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET (0x00)
|
||||
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET_BIT (2)
|
||||
|
||||
#define MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET (0x04)
|
||||
#define MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET (0x80)
|
||||
#define MIPI_CSI_DPHY_CTRL_SIG_INV_OFFSET (0x84)
|
||||
|
||||
/*Configure the count time of the THS-SETTLE by protocol.*/
|
||||
#define MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET (0x00)
|
||||
/*MSB enable for pin_rxdatahs_
|
||||
*1: enable
|
||||
*0: disable
|
||||
*/
|
||||
#define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38)
|
||||
|
||||
#define MIPI_CSI_DPHY_RX_FORCERXMODE_MASK (0x0f << 24)
|
||||
#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (8)
|
||||
|
||||
#define CSIHOST_N_LANES_OFFSET 0x04
|
||||
#define CSIHOST_N_LANES_OFFSET_BIT (0)
|
||||
|
||||
#define write_grf_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define read_grf_reg(addr) \
|
||||
__raw_readl((void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define mask_grf_reg(addr, msk, val) \
|
||||
write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
|
||||
|
||||
#define write_cru_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_cru_base))
|
||||
|
||||
/*#define cru_writel(v, o) do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
|
||||
* while (0)
|
||||
*/
|
||||
|
||||
#define write_csihost_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + phy_virt))
|
||||
#define read_csihost_reg(addr) \
|
||||
__raw_readl((void *)(addr + phy_virt))
|
||||
/*csi phy*/
|
||||
#define write_csiphy_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + csiphy_virt))
|
||||
#define read_csiphy_reg(addr) \
|
||||
__raw_readl((void *)(addr + csiphy_virt))
|
||||
|
||||
#endif
|
||||
@@ -1,427 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifdef CONFIG_ARM64
|
||||
#include "camsys_soc_priv.h"
|
||||
#include "camsys_soc_rk3399.h"
|
||||
|
||||
struct mipiphy_hsfreqrange_s {
|
||||
unsigned int range_l;
|
||||
unsigned int range_h;
|
||||
unsigned char cfg_bit;
|
||||
};
|
||||
|
||||
static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
|
||||
{80, 90, 0x00},
|
||||
{90, 100, 0x10},
|
||||
{100, 110, 0x20},
|
||||
{110, 130, 0x01},
|
||||
{130, 140, 0x11},
|
||||
{140, 150, 0x21},
|
||||
{150, 170, 0x02},
|
||||
{170, 180, 0x12},
|
||||
{180, 200, 0x22},
|
||||
{200, 220, 0x03},
|
||||
{220, 240, 0x13},
|
||||
{240, 250, 0x23},
|
||||
{250, 270, 0x04},
|
||||
{270, 300, 0x14},
|
||||
{300, 330, 0x05},
|
||||
{330, 360, 0x15},
|
||||
{360, 400, 0x25},
|
||||
{400, 450, 0x06},
|
||||
{450, 500, 0x16},
|
||||
{500, 550, 0x07},
|
||||
{550, 600, 0x17},
|
||||
{600, 650, 0x08},
|
||||
{650, 700, 0x18},
|
||||
{700, 750, 0x09},
|
||||
{750, 800, 0x19},
|
||||
{800, 850, 0x29},
|
||||
{850, 900, 0x39},
|
||||
{900, 950, 0x0a},
|
||||
{950, 1000, 0x1a},
|
||||
{1000, 1050, 0x2a},
|
||||
{1100, 1150, 0x3a},
|
||||
{1150, 1200, 0x0b},
|
||||
{1200, 1250, 0x1b},
|
||||
{1250, 1300, 0x2b},
|
||||
{1300, 1350, 0x0c},
|
||||
{1350, 1400, 0x1c},
|
||||
{1400, 1450, 0x2c},
|
||||
{1450, 1500, 0x3c}
|
||||
};
|
||||
|
||||
static char camsys_rk3399_mipiphy0_rd_reg(camsys_mipiphy_soc_para_t *para, unsigned char addr)
|
||||
{
|
||||
/*TESTCLK=1*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
|
||||
(1 << DPHY_RX0_TESTCLK_BIT));
|
||||
/*TESTEN =1,TESTDIN=addr*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
((addr << DPHY_RX0_TESTDIN_BIT) |
|
||||
DPHY_RX0_TESTDIN_MASK |
|
||||
(1 << DPHY_RX0_TESTEN_BIT) |
|
||||
DPHY_RX0_TESTEN_MASK));
|
||||
/*TESTCLK=0*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
|
||||
|
||||
return read_grf_reg(GRF_SOC_STATUS1)&0xff;
|
||||
}
|
||||
|
||||
static int camsys_rk3399_mipiphy0_wr_reg
|
||||
(camsys_mipiphy_soc_para_t *para, unsigned char addr, unsigned char data)
|
||||
{
|
||||
/*TESTCLK=1*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
|
||||
(1 << DPHY_RX0_TESTCLK_BIT));
|
||||
/*TESTEN =1,TESTDIN=addr*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
((addr << DPHY_RX0_TESTDIN_BIT) |
|
||||
DPHY_RX0_TESTDIN_MASK |
|
||||
(1 << DPHY_RX0_TESTEN_BIT) |
|
||||
DPHY_RX0_TESTEN_MASK));
|
||||
/*TESTCLK=0*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
|
||||
|
||||
if (data != 0xff) { /*write data ?*/
|
||||
/*TESTEN =0,TESTDIN=data*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
((data << DPHY_RX0_TESTDIN_BIT) |
|
||||
DPHY_RX0_TESTDIN_MASK |
|
||||
DPHY_RX0_TESTEN_MASK));
|
||||
|
||||
/*TESTCLK=1*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
|
||||
(1 << DPHY_RX0_TESTCLK_BIT));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static char camsys_rk3399_mipiphy1_wr_reg
|
||||
(unsigned long dsiphy_virt, unsigned char addr, unsigned char data)
|
||||
{
|
||||
/*TESTEN =1,TESTDIN=addr*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
|
||||
/*TESTCLK=0*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
|
||||
/*TESTEN =0,TESTDIN=data*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
|
||||
/*TESTCLK=1 */
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int camsys_rk3399_mipiphy1_rd_reg(unsigned long dsiphy_virt, unsigned char addr)
|
||||
{
|
||||
/*TESTEN =1,TESTDIN=addr*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
|
||||
/*TESTCLK=0*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
|
||||
return (read_dsihost_reg(DSIHOST_PHY_TEST_CTRL1)>>8);
|
||||
}
|
||||
|
||||
static int camsys_rk3399_mipihpy_cfg
|
||||
(camsys_mipiphy_soc_para_t *para)
|
||||
{
|
||||
unsigned char hsfreqrange = 0xff, i;
|
||||
struct mipiphy_hsfreqrange_s *hsfreqrange_p;
|
||||
unsigned long phy_virt, phy_index;
|
||||
unsigned long base;
|
||||
unsigned long csiphy_virt;
|
||||
unsigned long dsiphy_virt;
|
||||
unsigned long vir_base = 0;
|
||||
unsigned char settle_bypass = 0;
|
||||
unsigned char settle_en = 0;
|
||||
unsigned char manu_hsfreqrange = 0x04;
|
||||
|
||||
phy_index = para->phy->phy_index;
|
||||
if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
|
||||
phy_virt = para->camsys_dev->mipiphy[phy_index].reg->vir_base;
|
||||
} else {
|
||||
phy_virt = 0x00;
|
||||
}
|
||||
if (para->camsys_dev->csiphy_reg != NULL) {
|
||||
csiphy_virt =
|
||||
(unsigned long)para->camsys_dev->csiphy_reg->vir_base;
|
||||
} else {
|
||||
csiphy_virt = 0x00;
|
||||
}
|
||||
if (para->camsys_dev->dsiphy_reg != NULL) {
|
||||
dsiphy_virt =
|
||||
(unsigned long)para->camsys_dev->dsiphy_reg->vir_base;
|
||||
} else {
|
||||
dsiphy_virt = 0x00;
|
||||
}
|
||||
|
||||
if ((para->phy->bit_rate == 0) ||
|
||||
(para->phy->data_en_bit == 0)) {
|
||||
if (para->phy->phy_index == 0) {
|
||||
base =
|
||||
(para->camsys_dev->devmems.registermem->vir_base);
|
||||
*((unsigned int *)
|
||||
(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
|
||||
&= ~(0x0f << 8);
|
||||
camsys_trace(1, "mipi phy 0 standby!");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
hsfreqrange_p = mipiphy_hsfreqrange;
|
||||
for (i = 0;
|
||||
i < (sizeof(mipiphy_hsfreqrange)/
|
||||
sizeof(struct mipiphy_hsfreqrange_s));
|
||||
i++) {
|
||||
if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
|
||||
(para->phy->bit_rate <= hsfreqrange_p->range_h)) {
|
||||
hsfreqrange = hsfreqrange_p->cfg_bit;
|
||||
break;
|
||||
}
|
||||
hsfreqrange_p++;
|
||||
}
|
||||
|
||||
if (hsfreqrange == 0xff) {
|
||||
camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
|
||||
para->phy->bit_rate);
|
||||
hsfreqrange = 0x00;
|
||||
}
|
||||
hsfreqrange <<= 1;
|
||||
if (para->phy->phy_index == 0) {
|
||||
if (strstr(para->camsys_dev->miscdev.name, "camsys_marvin1")) {
|
||||
camsys_err("miscdev.name = %s,mipi phy index %d is invalidate\n",
|
||||
para->camsys_dev->miscdev.name,
|
||||
para->phy->phy_index);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
write_grf_reg(GRF_SOC_CON21_OFFSET,
|
||||
DPHY_RX0_FORCERXMODE_MASK |
|
||||
(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
|
||||
DPHY_RX0_FORCETXSTOPMODE_MASK |
|
||||
(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
|
||||
|
||||
/* set lane num*/
|
||||
write_grf_reg(GRF_SOC_CON21_OFFSET,
|
||||
DPHY_RX0_ENABLE_MASK |
|
||||
(para->phy->data_en_bit << DPHY_RX0_ENABLE_BIT));
|
||||
|
||||
/* set lan turndisab as 1*/
|
||||
write_grf_reg(GRF_SOC_CON21_OFFSET,
|
||||
DPHY_RX0_TURNDISABLE_MASK |
|
||||
(0xf << DPHY_RX0_TURNDISABLE_BIT));
|
||||
write_grf_reg(GRF_SOC_CON21_OFFSET, (0x0<<4) | (0xf<<20));
|
||||
|
||||
/* set lan turnrequest as 0 */
|
||||
write_grf_reg(GRF_SOC_CON9_OFFSET,
|
||||
DPHY_RX0_TURNREQUEST_MASK |
|
||||
(0x0 << DPHY_RX0_TURNREQUEST_BIT));
|
||||
|
||||
/*phy start*/
|
||||
{
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
DPHY_RX0_TESTCLK_MASK |
|
||||
(0x1 << DPHY_RX0_TESTCLK_BIT)); /*TESTCLK=1 */
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
DPHY_RX0_TESTCLR_MASK |
|
||||
(0x1 << DPHY_RX0_TESTCLR_BIT)); /*TESTCLR=1*/
|
||||
udelay(100);
|
||||
/*TESTCLR=0 zyc*/
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
DPHY_RX0_TESTCLR_MASK);
|
||||
udelay(100);
|
||||
/*set clock lane*/
|
||||
camsys_rk3399_mipiphy0_wr_reg
|
||||
(para, 0x34, settle_bypass);
|
||||
/*HS hsfreqrange & lane 0 settle bypass*/
|
||||
camsys_rk3399_mipiphy0_wr_reg
|
||||
(para, 0x44, hsfreqrange | settle_bypass);
|
||||
camsys_rk3399_mipiphy0_wr_reg
|
||||
(para, 0x54, settle_bypass);
|
||||
camsys_rk3399_mipiphy0_wr_reg
|
||||
(para, 0x84, settle_bypass);
|
||||
camsys_rk3399_mipiphy0_wr_reg
|
||||
(para, 0x94, settle_bypass);
|
||||
camsys_rk3399_mipiphy0_wr_reg
|
||||
(para, 0x75, (settle_en << 7) | manu_hsfreqrange);
|
||||
camsys_rk3399_mipiphy0_rd_reg(para, 0x75);
|
||||
/*Normal operation*/
|
||||
camsys_rk3399_mipiphy0_wr_reg(para, 0x0, -1);
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
DPHY_RX0_TESTCLK_MASK |
|
||||
(1 << DPHY_RX0_TESTCLK_BIT)); /*TESTCLK=1*/
|
||||
/*TESTEN =0 */
|
||||
write_grf_reg(GRF_SOC_CON25_OFFSET,
|
||||
(DPHY_RX0_TESTEN_MASK));
|
||||
}
|
||||
|
||||
base = (para->camsys_dev->devmems.registermem->vir_base);
|
||||
*((unsigned int *)(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL))) |=
|
||||
(0x0f<<8);
|
||||
|
||||
} else if (para->phy->phy_index == 1) {
|
||||
|
||||
if (!strstr(para->camsys_dev->miscdev.name, "camsys_marvin1")) {
|
||||
camsys_err
|
||||
("miscdev.name = %s,mipi phy index %d is invalidate\n",
|
||||
para->camsys_dev->miscdev.name,
|
||||
para->phy->phy_index);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
write_grf_reg(GRF_SOC_CON23_OFFSET,
|
||||
DPHY_RX0_FORCERXMODE_MASK |
|
||||
(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
|
||||
DPHY_RX0_FORCETXSTOPMODE_MASK |
|
||||
(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
|
||||
write_grf_reg(GRF_SOC_CON24_OFFSET,
|
||||
DPHY_TX1RX1_MASTERSLAVEZ_MASK |
|
||||
(0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
|
||||
DPHY_TX1RX1_BASEDIR_MASK |
|
||||
(0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
|
||||
DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
|
||||
|
||||
/* set lane num*/
|
||||
write_grf_reg(GRF_SOC_CON23_OFFSET,
|
||||
DPHY_TX1RX1_ENABLE_MASK |
|
||||
(para->phy->data_en_bit << DPHY_TX1RX1_ENABLE_BIT));
|
||||
|
||||
/* set lan turndisab as 1*/
|
||||
write_grf_reg(GRF_SOC_CON23_OFFSET,
|
||||
DPHY_TX1RX1_TURNDISABLE_MASK |
|
||||
(0xf << DPHY_TX1RX1_TURNDISABLE_BIT));
|
||||
write_grf_reg(GRF_SOC_CON23_OFFSET, (0x0<<4)|(0xf<<20));
|
||||
|
||||
/* set lan turnrequest as 0*/
|
||||
write_grf_reg(GRF_SOC_CON24_OFFSET,
|
||||
DPHY_TX1RX1_TURNREQUEST_MASK |
|
||||
(0x0 << DPHY_TX1RX1_TURNREQUEST_BIT));
|
||||
/*phy1 start*/
|
||||
{
|
||||
char res_val = 0;
|
||||
res_val = read_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ);
|
||||
res_val &= 0xfffffffe;
|
||||
/*SHUTDOWNZ=0*/
|
||||
write_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ, res_val);
|
||||
vir_base = (unsigned long)ioremap(0xff910000, 0x10000);
|
||||
/*__raw_writel(0x60000, (void*)(0x1c00+vir_base));*/
|
||||
res_val = 0;
|
||||
res_val = read_dsihost_reg(DSIHOST_DPHY_RSTZ);
|
||||
res_val &= 0xfffffffd;
|
||||
/*RSTZ=0*/
|
||||
write_dsihost_reg(DSIHOST_DPHY_RSTZ, res_val);
|
||||
/*TESTCLK=1*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
/*TESTCLR=1 TESTCLK=1 */
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000003);
|
||||
udelay(100);
|
||||
/*TESTCLR=0 TESTCLK=1*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
udelay(100);
|
||||
/*set clock lane*/
|
||||
camsys_rk3399_mipiphy1_wr_reg
|
||||
(dsiphy_virt, 0x34, settle_bypass);
|
||||
/*HS hsfreqrange & lane 0 settle bypass*/
|
||||
camsys_rk3399_mipiphy1_wr_reg
|
||||
(dsiphy_virt, 0x44, hsfreqrange | settle_bypass);
|
||||
camsys_rk3399_mipiphy1_wr_reg
|
||||
(dsiphy_virt, 0x54, settle_bypass);
|
||||
camsys_rk3399_mipiphy1_wr_reg
|
||||
(dsiphy_virt, 0x84, settle_bypass);
|
||||
camsys_rk3399_mipiphy1_wr_reg
|
||||
(dsiphy_virt, 0x94, settle_bypass);
|
||||
camsys_rk3399_mipiphy1_wr_reg
|
||||
(dsiphy_virt, 0x75, (settle_en << 7) | manu_hsfreqrange);
|
||||
camsys_rk3399_mipiphy1_rd_reg(dsiphy_virt, 0x75);
|
||||
/*TESTCLK=1*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
||||
/*TESTEN =0*/
|
||||
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000000);
|
||||
/*SHUTDOWNZ=1*//*RSTZ=1*/
|
||||
/*__raw_writel(0x60f00, (void*)(0x1c00+vir_base));*/
|
||||
write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000002);
|
||||
}
|
||||
|
||||
} else {
|
||||
camsys_err("mipi phy index %d is invalidate!",
|
||||
para->phy->phy_index);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",
|
||||
para->phy->phy_index, para->phy->data_en_bit,
|
||||
para->phy->bit_rate);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define MRV_AFM_BASE 0x0000
|
||||
#define VI_IRCL 0x0014
|
||||
int camsys_rk3399_cfg
|
||||
(camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
|
||||
{
|
||||
unsigned int *para_int;
|
||||
|
||||
switch (cfg_cmd) {
|
||||
case Clk_DriverStrength_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
__raw_writel((((*para_int) & 0x03) << 3) | (0x03 << 3),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x204));
|
||||
break;
|
||||
}
|
||||
|
||||
case Cif_IoDomain_Cfg: {
|
||||
para_int = (unsigned int *)cfg_para;
|
||||
if (*para_int < 28000000) {
|
||||
/* 1.8v IO */
|
||||
__raw_writel(((1 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0900));
|
||||
} else {
|
||||
/* 3.3v IO */
|
||||
__raw_writel(((0 << 1) | (1 << (1 + 16))),
|
||||
(void *)(camsys_dev->rk_grf_base + 0x0900));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Mipi_Phy_Cfg: {
|
||||
camsys_mipiphy_soc_para_t *para
|
||||
= (camsys_mipiphy_soc_para_t *)cfg_para;
|
||||
|
||||
if (para->phy->dir == CamSys_Mipiphy_Tx &&
|
||||
para->phy->phy_index == 1) {
|
||||
/* TX1/RX1 DPHY switch to RX status */
|
||||
__raw_writel(0x300020,
|
||||
(void *)(camsys_dev->rk_grf_base + 0x6260));
|
||||
} else {
|
||||
camsys_rk3399_mipihpy_cfg
|
||||
((camsys_mipiphy_soc_para_t *)cfg_para);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case Isp_SoftRst: /* ddl@rock-chips.com: v0.d.0 */ {
|
||||
unsigned long reset;
|
||||
reset = (unsigned long)cfg_para;
|
||||
|
||||
if (reset == 1)
|
||||
__raw_writel(0x80, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
else
|
||||
__raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
|
||||
MRV_AFM_BASE + VI_IRCL));
|
||||
break;
|
||||
}
|
||||
|
||||
default: {
|
||||
camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ARM64 */
|
||||
@@ -1,177 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RKCAMSYS_SOC_RK3399_H__
|
||||
#define __RKCAMSYS_SOC_RK3399_H__
|
||||
|
||||
#include "camsys_internal.h"
|
||||
|
||||
/*MARVIN REGISTER*/
|
||||
#define MRV_MIPI_BASE 0x1C00
|
||||
#define MRV_MIPI_CTRL 0x00
|
||||
|
||||
/*
|
||||
*#define CSIHOST_PHY_TEST_CTRL0_OFFSET 0x0030
|
||||
#define DPHY_TX1RX1_TESTCLR (1<<0)
|
||||
#define DPHY_TX1RX1_TESTCLK (1<<1)
|
||||
|
||||
#define CSIHOST_PHY_TEST_CTRL1_OFFSET 0x0034
|
||||
#define DPHY_TX1RX1_TESTDIN_OFFSET_BITS (0)
|
||||
#define DPHY_TX1RX1_TESTDOUT_OFFSET_BITS (8)
|
||||
#define DPHY_TX1RX1_TESTEN (16)
|
||||
*/
|
||||
|
||||
#define GRF_SOC_STATUS21 (0x2D4)
|
||||
#define GRF_SOC_STATUS1 (0x0e2a4)
|
||||
|
||||
#define CSIHOST_PHY_TEST_CTRL0 (0x30)
|
||||
#define CSIHOST_PHY_TEST_CTRL1 (0x34)
|
||||
#define CSIHOST_N_LANES (0x04)
|
||||
#define CSIHOST_PHY_SHUTDOWNZ (0x08)
|
||||
#define CSIHOST_CSI2_RESETN (0x10)
|
||||
#define CSIHOST_DPHY_RSTZ (0x0c)
|
||||
#define CSIHOST_PHY_STATE (0x14)
|
||||
#define CSIHOST_DATA_IDS1 (0x18)
|
||||
#define CSIHOST_DATA_IDS2 (0x1C)
|
||||
#define CSIHOST_ERR1 (0x20)
|
||||
#define CSIHOST_ERR2 (0x24)
|
||||
|
||||
/*
|
||||
*GRF_SOC_CON6
|
||||
*dphy_rx_forcerxmode 11:8
|
||||
*isp_mipi_csi_host_sel:1
|
||||
*disable_isp:0
|
||||
*bit 0 grf_con_disable_isp
|
||||
*bit 1 isp_mipi_csi_host_sel 1'b0: mipi csi host
|
||||
*/
|
||||
#define GRF_SOC_CON6_OFFSET (0x0418)
|
||||
/*bit 0*/
|
||||
#define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
|
||||
#define MIPI_PHY_DISABLE_ISP (0x0 << 0)
|
||||
/*bit 1*/
|
||||
#define ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK (0x1 << 17)
|
||||
#define ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT (0x1)
|
||||
/*bit 6*/
|
||||
#define DPHY_RX_CLK_INV_SEL_MASK (0x1 << 22)
|
||||
#define DPHY_RX_CLK_INV_SEL (0x1 << 6)
|
||||
/*bit 11:8*/
|
||||
#define DPHY_RX_FORCERXMODE_OFFSET_MASK (0xF << 24)
|
||||
#define DPHY_RX_FORCERXMODE_OFFSET_BITS (8)
|
||||
|
||||
/*GRF_SOC_CON7*/
|
||||
/*dphy_tx0_forcerxmode*/
|
||||
#define GRF_SOC_CON7_OFFSET (0x041c)
|
||||
/*bit 10:7*/
|
||||
#define FORCETXSTOPMODE_OFFSET_BITS (7)
|
||||
#define FORCETXSTOPMODE_MASK (0xF << 23)
|
||||
|
||||
#define DPHY_TX0_FORCERXMODE (6)
|
||||
#define DPHY_TX0_FORCERXMODE_MASK (0x01 << 22)
|
||||
/*bit 5*/
|
||||
#define LANE0_TURNDISABLE_BITS (5)
|
||||
#define LANE0_TURNDISABLE_MASK (0x01 << 21)
|
||||
|
||||
#define GRF_SOC_STATUS13 (0x04b4)
|
||||
|
||||
#define GRF_SOC_CON9_OFFSET (0x6224)
|
||||
#define DPHY_RX0_TURNREQUEST_MASK (0xF << 16)
|
||||
#define DPHY_RX0_TURNREQUEST_BIT (0)
|
||||
|
||||
#define GRF_SOC_CON21_OFFSET (0x6254)
|
||||
#define DPHY_RX0_FORCERXMODE_MASK (0xF << 20)
|
||||
#define DPHY_RX0_FORCERXMODE_BIT (4)
|
||||
#define DPHY_RX0_FORCETXSTOPMODE_MASK (0xF << 24)
|
||||
#define DPHY_RX0_FORCETXSTOPMODE_BIT (8)
|
||||
#define DPHY_RX0_TURNDISABLE_MASK (0xF << 28)
|
||||
#define DPHY_RX0_TURNDISABLE_BIT (12)
|
||||
#define DPHY_RX0_ENABLE_MASK (0xF << 16)
|
||||
#define DPHY_RX0_ENABLE_BIT (0)
|
||||
|
||||
#define GRF_SOC_CON23_OFFSET (0x625c)
|
||||
#define DPHY_TX1RX1_TURNDISABLE_MASK (0xF << 28)
|
||||
#define DPHY_TX1RX1_TURNDISABLE_BIT (12)
|
||||
#define DPHY_TX1RX1_FORCERXMODE_MASK (0xF << 20)
|
||||
#define DPHY_TX1RX1_FORCERXMODE_BIT (4)
|
||||
#define DPHY_TX1RX1_FORCETXSTOPMODE_MASK (0xF << 24)
|
||||
#define DPHY_TX1RX1_FORCETXSTOPMODE_BIT (8)
|
||||
#define DPHY_TX1RX1_ENABLE_MASK (0xF << 16)
|
||||
#define DPHY_TX1RX1_ENABLE_BIT (0)
|
||||
|
||||
#define GRF_SOC_CON24_OFFSET (0x6260)
|
||||
#define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 23)
|
||||
#define DPHY_TX1RX1_MASTERSLAVEZ_BIT (7)
|
||||
#define DPHY_TX1RX1_BASEDIR_MASK (0x1 << 21)
|
||||
#define DPHY_TX1RX1_BASEDIR_BIT (5)
|
||||
#define DPHY_RX1_MASK (0x1 << 20)
|
||||
#define DPHY_RX1_SEL_BIT (4)
|
||||
|
||||
#define DPHY_TX1RX1_TURNREQUEST_MASK (0xF << 16)
|
||||
#define DPHY_TX1RX1_TURNREQUEST_BIT (0)
|
||||
|
||||
#define GRF_SOC_CON25_OFFSET (0x6264)
|
||||
#define DPHY_RX0_TESTCLK_MASK (0x1 << 25)
|
||||
#define DPHY_RX0_TESTCLK_BIT (9)
|
||||
#define DPHY_RX0_TESTCLR_MASK (0x1 << 26)
|
||||
#define DPHY_RX0_TESTCLR_BIT (10)
|
||||
#define DPHY_RX0_TESTDIN_MASK (0xFF << 16)
|
||||
#define DPHY_RX0_TESTDIN_BIT (0)
|
||||
#define DPHY_RX0_TESTEN_MASK (0x1 << 24)
|
||||
#define DPHY_RX0_TESTEN_BIT (8)
|
||||
|
||||
/*dphy_rx_rxclkactivehs*/
|
||||
/*dphy_rx_direction*/
|
||||
/*dphy_rx_ulpsactivenot_0...3*/
|
||||
|
||||
/*LOW POWER MODE SET*/
|
||||
/*base*/
|
||||
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET (0x00)
|
||||
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET_BIT (2)
|
||||
|
||||
#define MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET (0x04)
|
||||
#define MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET (0x80)
|
||||
#define MIPI_CSI_DPHY_CTRL_SIG_INV_OFFSET (0x84)
|
||||
|
||||
/*Configure the count time of the THS-SETTLE by protocol.*/
|
||||
#define MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET (0x00)
|
||||
/*MSB enable for pin_rxdatahs_
|
||||
*1: enable
|
||||
*0: disable
|
||||
*/
|
||||
#define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38)
|
||||
|
||||
#define CSIHOST_N_LANES_OFFSET 0x04
|
||||
#define CSIHOST_N_LANES_OFFSET_BIT (0)
|
||||
|
||||
#define DSIHOST_PHY_SHUTDOWNZ (0x00a0)
|
||||
#define DSIHOST_DPHY_RSTZ (0x00a0)
|
||||
#define DSIHOST_PHY_TEST_CTRL0 (0x00b4)
|
||||
#define DSIHOST_PHY_TEST_CTRL1 (0x00b8)
|
||||
|
||||
#define write_grf_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define read_grf_reg(addr) \
|
||||
__raw_readl((void *)(addr + para->camsys_dev->rk_grf_base))
|
||||
#define mask_grf_reg(addr, msk, val) \
|
||||
write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
|
||||
|
||||
#define write_cru_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + para->camsys_dev->rk_cru_base))
|
||||
|
||||
/*#define cru_writel(v, o) do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
|
||||
* while (0)
|
||||
*/
|
||||
|
||||
#define write_csihost_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + phy_virt))
|
||||
#define read_csihost_reg(addr) \
|
||||
__raw_readl((void *)(addr + phy_virt))
|
||||
/*csi phy*/
|
||||
#define write_csiphy_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + csiphy_virt))
|
||||
#define read_csiphy_reg(addr) \
|
||||
__raw_readl((void *)(addr + csiphy_virt))
|
||||
|
||||
#define write_dsihost_reg(addr, val) \
|
||||
__raw_writel(val, (void *)(addr + dsiphy_virt))
|
||||
#define read_dsihost_reg(addr) \
|
||||
__raw_readl((void *)(addr + dsiphy_virt))
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user