From cfba10f2a1c88383606fa8f012ebf600272ad1ec Mon Sep 17 00:00:00 2001
From: Zhizhen Zheng <zhizhen.zheng@rock-chips.com>
Date: Wed, 12 Mar 2025 15:57:51 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b: add avsp node

Change-Id: Ia0e59d2a80261a38a233bed0d01f6082f184b828
Signed-off-by: Zhizhen Zheng <zhizhen.zheng@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 3ce3e372cba9..2e3a3bde598d 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -2226,6 +2226,29 @@
 		status = "disabled";
 	};
 
+	rkavsp: rkavsp@21f90000 {
+		compatible = "rockchip,rv1126b-rkavsp";
+		reg = <0x21f90000 0xf00>;
+		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "dcp_irq", "rcs_irq";
+		clocks = <&cru ACLK_AVSP>, <&cru HCLK_AVSP>;
+		clock-names = "aclk_avsp", "hclk_avsp";
+		iommus = <&rkavsp_mmu>;
+		status = "disabled";
+	};
+
+	rkavsp_mmu: iommu@21f90f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x21f90f00 0x100>;
+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "avsp_mmu";
+		clocks = <&cru ACLK_AVSP>, <&cru HCLK_AVSP>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+	};
+
 	rkaiisp: rkaiisp@21fa0000 {
 		compatible = "rockchip,rv1126b-rkaiisp";
 		reg = <0x21fa0000 0x3f00>;