From d0137fb9f31d9135ffa5964e5ab98f8a85f4ddb6 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 1 Jun 2022 10:11:41 +0800 Subject: [PATCH] clk: rockchip: pll: Don't power down pll when clk change fracdiv in rockchip_pll_clk_compensation() Fixes: 2a8e2fccde15 ("clk: rockchip: Add support for clk compensation") Signed-off-by: Finley Xiao Change-Id: I0c24a0e1b30a461d44bf74919f2cac44570bacc5 --- drivers/clk/rockchip/clk-pll.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 692334c58928..402548937f87 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -460,6 +460,7 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) #define RK3036_PLLCON1_DSMPD_MASK 0x1 #define RK3036_PLLCON1_DSMPD_SHIFT 12 #define RK3036_PLLCON1_PWRDOWN BIT(13) +#define RK3036_PLLCON1_PLLPDSEL BIT(15) #define RK3036_PLLCON2_FRAC_MASK 0xffffff #define RK3036_PLLCON2_FRAC_SHIFT 0 @@ -1525,6 +1526,10 @@ int rockchip_pll_clk_compensation(struct clk *clk, int ppm) fbdiv_mask = RK3036_PLLCON0_FBDIV_MASK; frac_mask = RK3036_PLLCON2_FRAC_MASK; frac_shift = RK3036_PLLCON2_FRAC_SHIFT; + if (!frac) + writel(HIWORD_UPDATE(RK3036_PLLCON1_PLLPDSEL, + RK3036_PLLCON1_PLLPDSEL, 0), + pll->reg_base + RK3036_PLLCON(1)); break; case pll_rk3066: return -EINVAL;