From d08def6b42758fee4048d6823e1a6ceacb09255e Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Mon, 22 Nov 2021 11:33:39 +0000 Subject: [PATCH] drm/rockchip: dsi2: config cphy lp2hs/hs2lp timing Change-Id: I37edc1aabc5592b2ab6453ea2bf966e82809947a Signed-off-by: Guochun Huang --- drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index 873d9c14b667..d12baaf1cc67 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -450,13 +450,14 @@ static void dw_mipi_dsi2_encoder_disable(struct drm_encoder *encoder) { struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder); - dw_mipi_dsi2_irq_enable(dsi2, 0); - if (dsi2->panel) drm_panel_disable(dsi2->panel); + dw_mipi_dsi2_disable(dsi2); + if (dsi2->panel) drm_panel_unprepare(dsi2->panel); + dw_mipi_dsi2_post_disable(dsi2); } @@ -592,10 +593,6 @@ static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) unsigned long long tmp, ui; unsigned long long hstx_clk; - /* test dphy firstly */ - if (dsi2->c_option) - return; - hstx_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * USEC_PER_SEC, 16); ui = ALIGN(PSEC_PER_SEC, hstx_clk);