From d090ed8f63e0723ae8e4935f7a9d1fd88c512042 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Mon, 13 Nov 2023 11:33:37 +0000 Subject: [PATCH] drm/rockchip/rk628: combtxphy: ref_clk should not be zero Change-Id: I395d721b2ab833fee6dfbdb53c6fc923f733a3d1 Signed-off-by: Guochun Huang --- drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c b/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c index 8cdb50cdf122..cbe7923139b7 100644 --- a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c +++ b/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c @@ -366,6 +366,10 @@ static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode, ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */ if (combtxphy->division_mode) ref_clk /= 2; + + if (!ref_clk) + return -EINVAL; + /* * the reference clock at PFD(FPFD = ref_clk / ref_div) about * 25MHz is recommende, FPFD must range from 16MHz to 35MHz,