From d0cca5a3d8de1d5937f2d3fc5ef0863f5b6988e2 Mon Sep 17 00:00:00 2001
From: Addy Ke <addy.ke@rock-chips.com>
Date: Mon, 28 Mar 2022 14:17:16 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588-toybrick-x0: enable pcie3x4

rk3588 toybrick board pcie3 have only 2 lanes.
set:
rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>;
num-lanes=<2>;

Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Change-Id: I3b0357a4a77aa00f578c32424b3bf11f5dd873e9
---
 arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi
index 2a9c94459b73..5e429e69ec44 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi
@@ -565,14 +565,15 @@
 };
 
 &pcie30phy {
-	rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
+	rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>;
 	status = "okay";
 };
 
 &pcie3x4 {
 	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie30>;
-	status = "disabled";
+	num-lanes=<2>;
+	status = "okay";
 };
 
 &pinctrl {