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phy: rockchip: naneng-combphy: fix U3 RX long cable test failed for RK3528

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1.Set slow slew rate control for PI
2.Set CDR phase path with 2x gain

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I2d0811b0be7b1d4764ecd738d069b06e4da5eaa2
This commit is contained in:
Jianwei Zheng
2023-08-10 17:20:39 +08:00
committed by Tao Huang
parent b59d476403
commit d0e6f8a073
1 changed files with 12 additions and 0 deletions
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12
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -483,6 +483,18 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
val |= 0x01 << 17; val |= 0x01 << 17;
writel(val, priv->mmio + 0x200); writel(val, priv->mmio + 0x200);
/* Set slow slew rate control for PI */
val = readl(priv->mmio + 0x204);
val &= ~GENMASK(2, 0);
val |= 0x07;
writel(val, priv->mmio + 0x204);
/* Set CDR phase path with 2x gain */
val = readl(priv->mmio + 0x204);
val &= ~GENMASK(5, 5);
val |= 0x01 << 5;
writel(val, priv->mmio + 0x204);
/* Set Rx squelch input filler bandwidth */ /* Set Rx squelch input filler bandwidth */
val = readl(priv->mmio + 0x20c); val = readl(priv->mmio + 0x20c);
val &= ~GENMASK(2, 0); val &= ~GENMASK(2, 0);