From d0eb5198e1fc1c485a339b4e0c168ff36e577508 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Wed, 13 Jul 2022 20:46:50 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588: Add hdmi reference to hdmiphy pll clock Signed-off-by: Algea Cao Change-Id: Ie3c154e151f4a5447cc0d6f94bcdfb86f5787c46 --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 8 +++++--- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 1ca30f9c1992..00a31afd5a87 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -415,7 +415,8 @@ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&hclk_vo1>; + <&hclk_vo1>, + <&hdptxphy_hdmi_clk1>; clock-names = "pclk", "hpd", "earc", @@ -425,7 +426,8 @@ "dclk_vp1", "dclk_vp2", "dclk_vp3", - "hclk_vo1"; + "hclk_vo1", + "link_clk"; resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; reset-names = "ref", "hdp"; power-domains = <&power RK3588_PD_VO1>; @@ -807,7 +809,7 @@ hdptxphy_hdmi_clk1: clk-port { #clock-cells = <0>; - status = "disabled"; + status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 9da438cde34e..9b1ecf16634c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -4124,7 +4124,8 @@ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&hclk_vo1>; + <&hclk_vo1>, + <&hdptxphy_hdmi_clk0>; clock-names = "pclk", "hpd", "earc", @@ -4134,7 +4135,8 @@ "dclk_vp1", "dclk_vp2", "dclk_vp3", - "hclk_vo1"; + "hclk_vo1", + "link_clk"; resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; reset-names = "ref", "hdp"; power-domains = <&power RK3588_PD_VO1>; @@ -5682,7 +5684,7 @@ hdptxphy_hdmi_clk0: clk-port { #clock-cells = <0>; - status = "disabled"; + status = "okay"; }; };