From d13ab488bbd3876bb75bd0dd29529522e7f964a6 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Tue, 9 Jul 2019 17:50:45 +0800 Subject: [PATCH] drm/rockchip: dsi: Fix improved D-PHY data lanes timing Change-Id: Ibc8dfd6bf208407117156dc36539d95740b213d8 Signed-off-by: Wyon Bi --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 30aa5975d507..cbd8ac0107cd 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -997,8 +997,8 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) { - regmap_write(dsi->regmap, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) | - PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); + regmap_write(dsi->regmap, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) | + PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); regmap_write(dsi->regmap, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));