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arm64: dts: rockchip: rk3588: add hdmirx_ctrler node
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com> Change-Id: I6d86ff13e58611e068fd3a6cc44d1f9b6f6457da
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@@ -50,6 +50,19 @@
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status = "disabled";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Reserve 128MB cma memory for hdmirx driver */
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hdmirx_reserved: hdmirx@10000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x10000000 0x0 (128 * 0x100000)>;
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status = "disabled";
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};
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};
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rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
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compatible = "rockchip,rkcif-mipi-lvds";
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rockchip,hw = <&rkcif>;
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@@ -462,6 +475,30 @@
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};
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};
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hdmirx_ctrler: hdmirx-controller@fdee0000 {
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compatible = "rk3588,hdmirx-ctrler", "rockchip,hdmirx-ctrler";
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reg = <0x0 0xfdee0000 0x0 0x6000>;
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reg-names = "hdmirx_regs";
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power-domains = <&power RK3588_PD_VO1>;
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rockchip,grf = <&sys_grf>;
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rockchip,vo1_grf = <&vo1_grf>;
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memory-region = <&hdmirx_reserved>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cec", "hdmi", "dma";
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clocks = <&cru ACLK_HDMIRX>, <&cru CLK_HDMIRX_AUD>,
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<&cru CLK_CR_PARA>, <&cru PCLK_HDMIRX>,
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<&cru CLK_HDMIRX_REF>, <&hclk_vo1>;
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clock-names = "aclk", "audio", "cr_para", "pclk", "ref", "hclk_vo1";
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resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
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<&cru SRST_HDMIRX_REF>;
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reset-names = "rst_a", "rst_p", "rst_ref";
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pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda>;
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pinctrl-names = "default";
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status = "disabled";
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};
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pcie3x4: pcie@fe150000 {
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compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
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#address-cells = <3>;
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