From d15b9a1449546fe69ff7d69ec78443816aa4f19b Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Wed, 22 Dec 2021 17:48:05 +0800
Subject: [PATCH] phy: rockchip: naneng-combphy: Renew detect bypass reg

Should use REG_19H instead of REG_DH.

Fixes: 2f06afaaa8f8 ("phy: rockchip: naneng-combphy: Force detect Rx for RK356X SoCs")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ifc9484e850955e6a36c30755a7ba1aee65070d0f
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index f3528251e297..0964d3ceec1d 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -142,9 +142,9 @@ static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
 	}
 
 	if (priv->cfg->force_det_out) {
-		val = readl(priv->mmio + (0xd << 2));
+		val = readl(priv->mmio + (0x19 << 2));
 		val |= BIT(5);
-		writel(val, priv->mmio + (0xd << 2));
+		writel(val, priv->mmio + (0x19 << 2));
 	}
 
 	return ret;