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rk3368: clk: fix rk3368 apll set_rate

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In rk3368, apll enter slow mode before changing settings
and return to normal mode after changing settings.

Signed-off-by: dkl <dkl@rock-chips.com>
This commit is contained in:
dkl
2014-12-13 12:00:23 +08:00
committed by Huang, Tao
parent f4c8e2cdac
commit d18042afb5
1 changed files with 14 additions and 18 deletions
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32
drivers/clk/rockchip/clk-pll.c
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@@ -2118,12 +2118,9 @@ static int clk_pll_set_rate_3368_apllb(struct clk_hw *hw, unsigned long rate,
CHANGE_APLL:
local_irq_save(flags);
/* If core src don't select gpll, apll need to enter slow mode
* before reset
*/
if (!sel_gpll)
cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
pll->mode_offset);
/* apll enter slow mode */
cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
pll->mode_offset);
/* PLL enter reset */
cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
@@ -2141,16 +2138,17 @@ CHANGE_APLL:
udelay(ps->rst_dly);
pll_wait_lock(hw);
/* PLL return from slow mode */
if (!sel_gpll) {
if (rate >= old_rate) {
cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
}
cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
pll->mode_offset);
}
/* apll return from slow mode */
cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
pll->mode_offset);
/* reparent to apll, and set div to 1 */
if (sel_gpll) {
#if RK3368_APLLB_DIV_MORE
@@ -2347,12 +2345,9 @@ static int clk_pll_set_rate_3368_aplll(struct clk_hw *hw, unsigned long rate,
CHANGE_APLL:
local_irq_save(flags);
/* If core src don't select gpll, apll need to enter slow mode
* before reset
*/
if (!sel_gpll)
cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
pll->mode_offset);
/* apll enter slow mode */
cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
pll->mode_offset);
/* PLL enter reset */
cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
@@ -2370,16 +2365,17 @@ CHANGE_APLL:
udelay(ps->rst_dly);
pll_wait_lock(hw);
/* PLL return from slow mode */
if (!sel_gpll) {
if (rate >= old_rate) {
cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
}
cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
pll->mode_offset);
}
/* apll return from slow mode */
cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
pll->mode_offset);
/* reparent to apll, and set div to 1 */
if (sel_gpll) {
#if RK3368_APLLL_DIV_MORE