From d1917fb49258288b7d95f2bfa8fbdb172387e55e Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Fri, 11 Aug 2017 09:51:08 +0800 Subject: [PATCH] drm/rockchip: vop: correct dclk_ddr define for rk3368 dclk_ddr is supported on rk3368 vop, it would effect the display quality on YUV420 mode. Change-Id: Ia624a1f397e732d80d3908b8e712ae79d3ad7948 Signed-off-by: Mark Yao Reported-by: Huacong Yang --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 1f6241e8a216..7bc5cb42e3d9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -190,7 +190,7 @@ static const struct vop_ctrl rk3288_ctrl_data = { .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), .core_dclk_div = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 4, 3, 4, -1), .p2i_en = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 5, 3, 4, -1), - .dclk_ddr = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 8, 3, 4, -1), + .dclk_ddr = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 8, 3, 2, -1), .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),