From d1eddae5c0c7444d175b921d6434bb9ddbfa050b Mon Sep 17 00:00:00 2001 From: Brian Zhu Date: Mon, 3 Dec 2018 22:04:24 +0800 Subject: [PATCH] vpp: sr: remove the vpp misc operation in sr function [1/1] PD#SWPL-2613 Problem: sr mux in vpp misc is set incorrectly. Solution: move the vpp misc operation together Verify: verify by x301 Change-Id: Ie813e5b04b97a4481c2e45bcf0c8b4c065fb9f69 Signed-off-by: Brian Zhu --- drivers/amlogic/media/video_sink/video.c | 27 ++++++ drivers/amlogic/media/video_sink/vpp.c | 94 +++++++++++++------ .../linux/amlogic/media/video_sink/video.h | 4 + include/linux/amlogic/media/video_sink/vpp.h | 4 + 4 files changed, 100 insertions(+), 29 deletions(-) diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c index cba601624e1e..f4a70fe4e64e 100644 --- a/drivers/amlogic/media/video_sink/video.c +++ b/drivers/amlogic/media/video_sink/video.c @@ -6487,6 +6487,33 @@ SET_FILTER: if (!legacy_vpp) { u32 set_value = 0; + /* for sr core0, put it between prebld & pps as default */ + if (cur_frame_par && + (cur_frame_par->sr_core_support & + SUPER_CORE0_SUPPORT)) + if (cur_frame_par->sr0_position) + vpp_misc_set |= + PREBLD_SR0_VD1_SCALER; + else + vpp_misc_set &= + ~SR0_AFTER_DNLP; + else + vpp_misc_set |= + PREBLD_SR0_VD1_SCALER; + /* for sr core1, put it before post blend as default */ + if (cur_frame_par && + (cur_frame_par->sr_core_support & + SUPER_CORE1_SUPPORT)) + if (cur_frame_par->sr1_position) + vpp_misc_set |= + DNLP_SR1_CM; + else + vpp_misc_set &= + ~SR1_AFTER_POSTBLEN; + else + vpp_misc_set |= + DNLP_SR1_CM; + vpp_misc_set &= ((1 << 29) | VPP_CM_ENABLE | (0x1ff << VPP_VD2_ALPHA_BIT) | diff --git a/drivers/amlogic/media/video_sink/vpp.c b/drivers/amlogic/media/video_sink/vpp.c index 17d138499af4..8bfb6824ff02 100644 --- a/drivers/amlogic/media/video_sink/vpp.c +++ b/drivers/amlogic/media/video_sink/vpp.c @@ -1818,39 +1818,16 @@ int vpp_set_super_scaler_regs(int scaler_path_sel, data_path_chose = 6; else data_path_chose = 5; - if (is_meson_tl1_cpu()) { - if (scaler_path_sel == CORE0_PPS_CORE1) { - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 1, 1); - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 3, 1); - } else if (scaler_path_sel == CORE0_CORE1_PPS) { - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 1, 1); - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 3, 1); - - } else if (scaler_path_sel == PPS_CORE0_CORE1) { - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 1, 1); - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 3, 1); - - } else if (scaler_path_sel == PPS_CORE0_POSTBLEND_CORE1) { - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 1, 1); - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 3, 1); - } - } else if ((scaler_path_sel == CORE0_PPS_CORE1) || - (scaler_path_sel == CORE1_BEFORE_PPS) || - (scaler_path_sel == CORE0_BEFORE_PPS)) { - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 1, 1); - else + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_TXHD) { + if ((scaler_path_sel == CORE0_PPS_CORE1) || + (scaler_path_sel == CORE1_BEFORE_PPS) || + (scaler_path_sel == CORE0_BEFORE_PPS)) { VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL, 0, data_path_chose, 1); - } else { - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) { - if (scaler_path_sel == CORE0_AFTER_PPS) - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 1, 1); - else - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 1, 1); - } else + } else { VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL, 1, data_path_chose, 1); + } } if (super_scaler == 0) { VSYNC_WR_MPEG_REG(VPP_SRSHARP0_CTRL, 0); @@ -1871,10 +1848,13 @@ static void vpp_set_super_scaler(const struct vinfo_s *vinfo, next_frame_par->VPP_vsc_startp + 1; u32 src_width = next_frame_par->video_input_w; u32 src_height = next_frame_par->video_input_h; + u32 sr_path; /*for sr adjust*/ vpp_super_scaler_support(); + next_frame_par->sr_core_support = sr_support; + hor_sc_multiple_num = (1 << PPS_FRAC_BITS) / next_frame_par->vpp_filter.vpp_hsc_start_phase_step; ver_sc_multiple_num = SUPER_SCALER_V_FACTOR*(1 << PPS_FRAC_BITS)/ @@ -2180,6 +2160,62 @@ static void vpp_set_super_scaler(const struct vinfo_s *vinfo, next_frame_par->VPP_pic_in_height_ <<= next_frame_par->supsc1_vert_ratio; } + + sr_path = next_frame_par->supscl_path; + /* path config */ + if (is_meson_tl1_cpu()) { + if (sr_path == CORE0_PPS_CORE1) { + next_frame_par->sr0_position = 1; + next_frame_par->sr1_position = 1; + } else if (sr_path == PPS_CORE0_CORE1) { + next_frame_par->sr0_position = 0; + next_frame_par->sr1_position = 1; + } else if (sr_path == + PPS_CORE0_POSTBLEND_CORE1) { + next_frame_par->sr0_position = 0; + next_frame_par->sr1_position = 0; + } else if (sr_path == + CORE0_PPS_POSTBLEND_CORE1) { + next_frame_par->sr0_position = 1; + next_frame_par->sr1_position = 0; + } else { + next_frame_par->sr0_position = 1; + next_frame_par->sr1_position = 1; + } + } else if (is_meson_txhd_cpu() + || is_meson_g12a_cpu() + || is_meson_g12b_cpu()) { + if (sr_path == CORE0_BEFORE_PPS) + next_frame_par->sr0_position = 1; + else if (sr_path == CORE0_AFTER_PPS) + next_frame_par->sr0_position = 0; + else + next_frame_par->sr0_position = 1; + next_frame_par->sr1_position = 0; + } else if (is_meson_gxlx_cpu()) { + if (sr_path == CORE1_BEFORE_PPS) + next_frame_par->sr1_position = 1; + else if (sr_path == CORE1_AFTER_PPS) + next_frame_par->sr1_position = 0; + else + next_frame_par->sr1_position = 1; + next_frame_par->sr0_position = 0; + } else if (is_meson_txlx_cpu() + || is_meson_txl_cpu() + || is_meson_gxtvbb_cpu()) { + if (sr_path == CORE0_PPS_CORE1) { + next_frame_par->sr0_position = 1; + next_frame_par->sr1_position = 1; + } else if (sr_path == + CORE0_PPS_POSTBLEND_CORE1) { + next_frame_par->sr0_position = 1; + next_frame_par->sr1_position = 0; + } else { + next_frame_par->sr0_position = 1; + next_frame_par->sr1_position = 1; + } + } + if (super_debug) { pr_info("spsc0_w_in=%u, spsc0_h_in=%u, spsc1_w_in=%u, spsc1_h_in=%u.\n", next_frame_par->spsc0_w_in, next_frame_par->spsc0_h_in, diff --git a/include/linux/amlogic/media/video_sink/video.h b/include/linux/amlogic/media/video_sink/video.h index 548fcea8d7fa..07a2c01395ff 100644 --- a/include/linux/amlogic/media/video_sink/video.h +++ b/include/linux/amlogic/media/video_sink/video.h @@ -97,7 +97,11 @@ extern bool super_scaler; #define VPP_POST_FG_SEL_MASK (1 << 4) #define VPP_POST_FG_OSD2 (1 << 4) #define VPP_POST_FG_OSD1 (0 << 4) +#define DNLP_SR1_CM (1 << 3) +#define SR1_AFTER_POSTBLEN (0 << 3) #define VPP_FIFO_RESET_DE (1 << 2) +#define PREBLD_SR0_VD1_SCALER (1 << 1) +#define SR0_AFTER_DNLP (0 << 1) #define VPP_OUT_SATURATE (1 << 0) #define VDIF_RESET_ON_GO_FIELD (1<<29) diff --git a/include/linux/amlogic/media/video_sink/vpp.h b/include/linux/amlogic/media/video_sink/vpp.h index 8f2c7db79ec9..77e9e27a4049 100644 --- a/include/linux/amlogic/media/video_sink/vpp.h +++ b/include/linux/amlogic/media/video_sink/vpp.h @@ -140,6 +140,9 @@ struct vpp_frame_par_s { bool nocomp; + u8 sr0_position; + u8 sr1_position; + u8 sr_core_support; }; #if 1 @@ -170,6 +173,7 @@ enum select_scaler_path_e { /*tl1 have core0/core1, support below mode*/ PPS_CORE0_CORE1, PPS_CORE0_POSTBLEND_CORE1, + CORE0_PPS_POSTBLEND_CORE1, SCALER_PATH_MAX, }; /*