From d1fe482eeca6c319b963be8d9a839eaba3a50365 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Fri, 24 Jun 2022 16:14:20 +0800 Subject: [PATCH] drm/rockchop: vop2: set extend clk vp mask When a extend clk is used before enter kernel, it need set the vp mask to mark that it have been used by a video port Signed-off-by: Zhang Yubing Change-Id: Ie6f0419621e8b250adca1783355318d4a9a2412d --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index c5c7bd219ea1..e53b0b5caf24 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -5163,6 +5163,9 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on) struct drm_crtc_state *crtc_state; struct drm_display_mode *mode; struct vop2_win *win, *splice_win; + struct vop2_extend_pll *ext_pll; + struct clk *parent_clk; + const char *clk_name; if (on == vp->loader_protect) return 0; @@ -5200,6 +5203,17 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on) } } } + parent_clk = clk_get_parent(vp->dclk); + clk_name = __clk_get_name(parent_clk); + if (!strcmp(clk_name, "clk_hdmiphy_pixel0")) { + ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll"); + if (ext_pll) + ext_pll->vp_mask |= BIT(vp->id); + } else if (!strcmp(clk_name, "clk_hdmiphy_pixel1")) { + ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"); + if (ext_pll) + ext_pll->vp_mask |= BIT(vp->id); + } drm_crtc_vblank_on(crtc); if (private->cubic_lut[vp->id].enable) { dma_addr_t cubic_lut_mst;