From d24ea079f0d33beebec9c9c7a6e61e81321ea99a Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 20 Dec 2018 15:02:50 +0800 Subject: [PATCH] clk: rockchip: rk3188: add FRAC_MAX_PRATE limit for spdif/uart/i2s/hsadc Change-Id: I32d2d1868674c0067bc32ae3a2ece0de7c71fe93 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3188.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 56a1ba236ddf..4f9f59b62d58 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -22,6 +22,10 @@ #define RK3066_GRF_SOC_STATUS 0x15c #define RK3188_GRF_SOC_STATUS 0xac +#define RK3188_UART_FRAC_MAX_PRATE 600000000 +#define RK3188_I2S_FRAC_MAX_PRATE 600000000 +#define RK3188_SPDIF_FRAC_MAX_PRATE 600000000 +#define RK3188_HSADC_FRAC_MAX_PRATE 300000000 enum rk3188_plls { apll, cpll, dpll, gpll, @@ -370,7 +374,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0, RK2928_CLKSEL_CON(23), 0, RK2928_CLKGATE_CON(2), 7, GFLAGS, - &common_hsadc_out_fracmux, 0), + &common_hsadc_out_fracmux, RK3188_HSADC_FRAC_MAX_PRATE), INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", RK2928_CLKSEL_CON(22), 7, IFLAGS), @@ -384,7 +388,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 0, RK2928_CLKGATE_CON(0), 14, GFLAGS, - &common_spdif_fracmux, 0), + &common_spdif_fracmux, RK3188_SPDIF_FRAC_MAX_PRATE), /* * Clock-Architecture Diagram 4 @@ -418,28 +422,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0, RK2928_CLKSEL_CON(17), 0, RK2928_CLKGATE_CON(1), 9, GFLAGS, - &common_uart0_fracmux, 0), + &common_uart0_fracmux, RK3188_UART_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0, RK2928_CLKSEL_CON(18), 0, RK2928_CLKGATE_CON(1), 11, GFLAGS, - &common_uart1_fracmux, 0), + &common_uart1_fracmux, RK3188_UART_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0, RK2928_CLKSEL_CON(19), 0, RK2928_CLKGATE_CON(1), 13, GFLAGS, - &common_uart2_fracmux, 0), + &common_uart2_fracmux, RK3188_UART_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 14, GFLAGS), COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0, RK2928_CLKSEL_CON(20), 0, RK2928_CLKGATE_CON(1), 15, GFLAGS, - &common_uart3_fracmux, 0), + &common_uart3_fracmux, RK3188_UART_FRAC_MAX_PRATE), GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), @@ -625,21 +629,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0, RK2928_CLKSEL_CON(6), 0, RK2928_CLKGATE_CON(0), 8, GFLAGS, - &rk3066a_i2s0_fracmux, 0), + &rk3066a_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0, RK2928_CLKSEL_CON(7), 0, RK2928_CLKGATE_CON(0), 10, GFLAGS, - &rk3066a_i2s1_fracmux, 0), + &rk3066a_i2s1_fracmux, RK3188_I2S_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 11, GFLAGS), COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0, RK2928_CLKSEL_CON(8), 0, RK2928_CLKGATE_CON(0), 12, GFLAGS, - &rk3066a_i2s2_fracmux, 0), + &rk3066a_i2s2_fracmux, RK3188_I2S_FRAC_MAX_PRATE), GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), @@ -733,7 +737,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0, RK2928_CLKSEL_CON(7), 0, RK2928_CLKGATE_CON(0), 10, GFLAGS, - &rk3188_i2s0_fracmux, 0), + &rk3188_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE), GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),