From d28c2096be7a6ff4554a69df58f07ef472c16942 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 23 Jul 2024 17:27:52 +0800 Subject: [PATCH] ARM: dts: rockchip: rk3506: add osc clk configs for pwm0 For rk3506, pwm0 supports wave generator mode, which relies on the osc clk. Change-Id: I8897595eeda31b0f606c2f2f6a365a1125fceeac Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 52a723b2ed26..ed5973b44065 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -1592,8 +1592,8 @@ compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; reg = <0xff930000 0x200>; interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; #pwm-cells = <3>; status = "disabled"; }; @@ -1602,8 +1602,8 @@ compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; reg = <0xff931000 0x200>; interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; #pwm-cells = <3>; status = "disabled"; }; @@ -1612,8 +1612,8 @@ compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; reg = <0xff932000 0x200>; interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; #pwm-cells = <3>; status = "disabled"; }; @@ -1622,8 +1622,8 @@ compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; reg = <0xff933000 0x200>; interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; #pwm-cells = <3>; status = "disabled"; };