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drm/bridge: tc358768: fix PLL parameters computation
[ Upstream commit6a4020b4c6] According to Toshiba documentation the PLL input clock after the divider should be not less than 4MHz, fix the PLL parameters computation accordingly. Fixes:ff1ca6397b("drm/bridge: Add tc358768 driver") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230427142934.55435-3-francesco@dolcini.it Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
c4cf126320
commit
d2aad3c1e4
@@ -335,13 +335,17 @@ static int tc358768_calc_pll(struct tc358768_priv *priv,
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u32 fbd;
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u32 fbd;
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for (fbd = 0; fbd < 512; ++fbd) {
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for (fbd = 0; fbd < 512; ++fbd) {
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u32 pll, diff;
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u32 pll, diff, pll_in;
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pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
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pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
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if (pll >= max_pll || pll < min_pll)
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if (pll >= max_pll || pll < min_pll)
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continue;
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continue;
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pll_in = (u32)div_u64((u64)refclk, prd + 1);
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if (pll_in < 4000000)
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continue;
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diff = max(pll, target_pll) - min(pll, target_pll);
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diff = max(pll, target_pll) - min(pll, target_pll);
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if (diff < best_diff) {
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if (diff < best_diff) {
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