From d2bc46a7035c7ef528e57f4e481bb0d3a662f9f8 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Thu, 24 May 2018 14:50:45 +0800 Subject: [PATCH] ARM: rockchip: support CPU config CACHE_L2X0/TWD/ARM_GLOBAL_TIMER are only available on Cortex-A9. DW_APB_TIMER_OF only use on rk3066a. Change-Id: Ied2f49b5d308e961ce5af72eb577aac23e3eb890 Signed-off-by: Tao Huang --- arch/arm/mach-rockchip/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6b6eb0f2b4e9..a929f0f787bd 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -7,15 +7,15 @@ config ARCH_ROCKCHIP select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select ARM_GIC - select CACHE_L2X0 + select CACHE_L2X0 if (CPU_RK30XX || CPU_RK3188) select HAVE_ARM_ARCH_TIMER select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP - select DW_APB_TIMER_OF + select HAVE_ARM_TWD if SMP && (CPU_RK30XX || CPU_RK3188) + select DW_APB_TIMER_OF if CPU_RK30XX select REGULATOR if PM select ROCKCHIP_TIMER - select ARM_GLOBAL_TIMER - select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK + select ARM_GLOBAL_TIMER if (CPU_RK30XX || CPU_RK3188) + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK if (CPU_RK30XX || CPU_RK3188) select ZONE_DMA if ARM_LPAE help Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs