From d3528bf2ff81f34b9a3edb913aed2f6b5f2e9fd7 Mon Sep 17 00:00:00 2001 From: William Wu Date: Thu, 30 May 2019 15:59:41 +0800 Subject: [PATCH] phy: rockchip-inno-combphy: tuning lane 0 TX driver swing for usb This patch tuning lane 0 TX driver swing for USB 3.0 to get larger swing for LFPS. Test on RK1808-stick board: offset[0x21b8] 5G LFPS Peak-Peak Differential Output Voltage 0xd9 Actual Value: 807.9mv Margin: 2.0% 0xe9 Actual Value: 832.2mv Margin: 8.1% 0xf9 Actual Value: 842.7mv Margin: 10.7% We set PHY register offset[0x21b8] to 0xe9 in this patch. Change-Id: Ic1878fbea5c0b67ce943544e9d9afdf912341b45 Signed-off-by: William Wu --- drivers/phy/rockchip/phy-rockchip-inno-combphy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c index 29a166d3a4da..bd91ef1a52d1 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c @@ -889,7 +889,7 @@ static int rk1808_combphy_cfg(struct rockchip_combphy_priv *priv) * largest swing and "0000" the smallest. */ reg = readl(priv->mmio + 0x21b8); - reg = (reg & ~0xf0) | 0xa0; + reg = (reg & ~0xf0) | 0xe0; writel(reg, priv->mmio + 0x21b8); /*