From d368d1acda6aca43ce4659be4e19316a4e818650 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 28 Mar 2019 14:37:04 +0800 Subject: [PATCH] clk: rockchip: rk3288: Add 420MHz for PLL Change-Id: Ic722bdf5d467a64cdf093f8bdabb6dab533cd230 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3288.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 7fe62a65007d..d17fa551c153 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -92,6 +92,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 500000000, 1, 125, 6), RK3066_PLL_RATE( 456000000, 1, 76, 4), + RK3066_PLL_RATE( 420000000, 1, 70, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), RK3066_PLL_RATE( 400000000, 1, 100, 6), RK3066_PLL_RATE( 384000000, 1, 64, 4),