From d38988a104bf4a2476fefbca264786a28e22734d Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 9 Dec 2020 10:28:20 +0800 Subject: [PATCH] PCI: rockchip: dw: decrease linking timeout to 10s The original waiting time is too long for setting up a link, so let's decrease it to 10s which is enough for real usecase. Change-Id: Ifb1eb0d7784e9afeef165f084bc3bda49b41618e Signed-off-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 03cff6fd83db..8f00c16f3553 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -451,7 +451,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci) /* Enable LTSSM */ rk_pcie_enable_ltssm(rk_pcie); - for (retries = 0; retries < 1000000; retries++) { + for (retries = 0; retries < 10; retries++) { if (dw_pcie_link_up(pci)) { dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n", rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); @@ -462,7 +462,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci) dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n", rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); rk_pcie_debug_dump(rk_pcie); - mdelay(1000); + msleep(1000); } dev_err(pci->dev, "PCIe Link Fail\n");