From d41cbb73cbee2eccff3a37a85f1fbf79fce2ee57 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 22 Dec 2021 10:41:30 +0800 Subject: [PATCH] PCI: rockchip: dw: Reduce establish linking time We kick probe to a kthread so giving a more generous timing would not be a problem. But given that it's the same routine for resume, we need more limited timing. Signed-off-by: Shawn Lin Change-Id: I382bb07ffa389caf854d725c955220c65366cd36 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 6b3d63faa901..cc7141d880f7 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -716,12 +716,12 @@ static int rk_pcie_establish_link(struct dw_pcie *pci) * PERST and T_PVPERL (Power stable to PERST# inactive) should be a * minimum of 100ms. See table 2-4 in section 2.6.2 AC, the PCI Express * Card Electromechanical Specification 3.0. So 100ms in total is the min - * requuirement here. We add a 1s for sake of hoping everthings work fine. + * requuirement here. We add a 200ms for sake of hoping everthings work fine. */ - msleep(1000); + msleep(200); gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1); - for (retries = 0; retries < 10; retries++) { + for (retries = 0; retries < 100; retries++) { if (dw_pcie_link_up(pci)) { /* * We may be here in case of L0 in Gen1. But if EP is capable @@ -730,7 +730,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci) * that LTSSM max timeout is 24ms per period, we can wait a bit * more for Gen switch. */ - msleep(100); + msleep(50); dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n", rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); rk_pcie_debug_dump(rk_pcie); @@ -740,7 +740,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci) dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n", rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); rk_pcie_debug_dump(rk_pcie); - msleep(1000); + msleep(20); } dev_err(pci->dev, "PCIe Link Fail\n");