From d48ecfc5f703b5c764f15829202cf6131ea51d76 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 19 May 2023 09:35:01 +0800 Subject: [PATCH] phy: rockchip: mipi csi2 dphy fixes grf write error of val for lane select Signed-off-by: Zefa Chen Change-Id: Id56eb83d9a25c15b9d611232e6f82221a55c7e64 --- drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c index 92f1174a99e6..e0a9fd65c16b 100644 --- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c +++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c @@ -572,7 +572,7 @@ static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy, is_cif = false; if (hw->lane_mode == LANE_MODE_FULL) { - val = ~GRF_CSI2PHY_LANE_SEL_SPLIT; + val = !GRF_CSI2PHY_LANE_SEL_SPLIT; if (dphy->phy_index < 3) { write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0));