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RK3188:ddr_clock select GPLL_2_div if ddr_freq big then 250MHz,

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only use for DPLL bad and ddr_clock must select GPLL(800MHz-1000MHz).
This commit is contained in:
cym
2013-05-13 16:40:25 +08:00
parent d24c73a5fd
commit d4d25daaff
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-rk30/ddr.c Normal file → Executable file
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@@ -3717,7 +3717,7 @@ uint32_t ddr_change_freq(uint32_t nMHz)
}
else if(gpllvaluel > 800) //GPLL:800MHz-1000MHz
{
if(nMHz > 300)
if(nMHz > 250)
ddr_select_gpll_div=2; //DDR_CLCOK:400MHz-500MHz
else
ddr_select_gpll_div=4; //DDR_CLCOK:200MHz-250MHz