From d4f4e5cea6961be442ba847e42f7c468f9ff1fac Mon Sep 17 00:00:00 2001 From: Jianhui Wang Date: Sun, 14 Nov 2021 10:01:37 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s-tablet: bring up tablet Signed-off-by: Jianhui Wang Change-Id: I6601901251c535240b4a2cad6f4ea4bc22494ff8 --- .../boot/dts/rockchip/rk3588s-tablet.dtsi | 137 +++++++++++++++++- 1 file changed, 130 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi index 3f2f206847dd..08d291de7613 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "rk3588s.dtsi" #include "rk3588-android.dtsi" @@ -26,13 +27,13 @@ vol-up-key { label = "volume up"; linux,code = ; - press-threshold-microvolt = <1750>; + press-threshold-microvolt = <17000>; }; vol-down-key { label = "volume down"; linux,code = ; - press-threshold-microvolt = <297500>; + press-threshold-microvolt = <417000>; }; }; @@ -102,6 +103,40 @@ status = "okay"; }; + panel-edp { + compatible = "innolux,p120zdg-bf4", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <500>; + disable-delay-ms = <120>; + width-mm = <254>; + height-mm = <169>; + + panel-timing { + clock-frequency = <206000000>; + hactive = <2160>; + vactive = <1440>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <10>; + vback-porch = <27>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + rk_headset: rk-headset { status = "disabled"; compatible = "rockchip_headset"; @@ -115,13 +150,21 @@ status = "okay"; }; + vcc3v3_lcd_edp: vcc3v3-lcd-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_edp"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc_3v3_s3>; + }; + vbus5v0_typec: vbus-typec { compatible = "regulator-fixed"; regulator-name = "vbus5v0_typec"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; vin-supply = <&vcc5v0_usb>; pinctrl-names = "default"; pinctrl-0 = <&typec5v_pwren>; @@ -160,10 +203,52 @@ }; }; +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + &fiq_debugger { pinctrl-0 = <&uart2m1_xfer>; }; +&gpu { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c2 { status = "okay"; @@ -175,7 +260,7 @@ pinctrl-0 = <&rtc_int>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; }; cw2015@62 { @@ -378,7 +463,7 @@ headphone { hp_det: hp-det { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -414,15 +499,20 @@ usb-typec { usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; }; typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + &saradc { status = "okay"; vref-supply = <&avcc_1v8_s0>; @@ -571,6 +661,7 @@ &usbdrd_dwc3_0 { dr_mode = "peripheral"; + maximum-speed = "high-speed"; status = "okay"; usb-role-switch; @@ -591,3 +682,35 @@ &usbhost_dwc3_0 { status = "disabled"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP2_SRC>, <&cru DCLK_VOP2_SRC>, + <&cru DCLK_VOP2_SRC>, <&cru DCLK_VOP3>; + assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +};