shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 12:17:12 +09:00
Code Issues Packages Projects Releases Wiki Activity

media: rockchip: isp: default reg config after reset

Browse Source 
Change-Id: Ib1e26819a1abfa74c072925af5dbb1ad7ec451f4
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2022-09-07 14:13:30 +08:00
committed by Tao Huang
parent 5316507f75
commit d4f6aaf7bc
2 changed files with 32 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -594,7 +594,15 @@ static inline bool is_iommu_enable(struct device *dev)
void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
{
void __iomem *base = dev->base_addr;
u32 val;
u32 val, iccl0, iccl1, clk_ctrl0, clk_ctrl1;
/* record clk config and recover */
iccl0 = readl(base + CIF_ICCL);
clk_ctrl0 = readl(base + CTRL_VI_ISP_CLK_CTRL);
if (dev->is_unite) {
iccl1 = readl(dev->base_next_addr + CIF_ICCL);
clk_ctrl1 = readl(dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
}
if (is_secure) {
/* if isp working, cru reset isn't secure.
@@ -633,6 +641,29 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
rockchip_iommu_disable(dev->dev);
rockchip_iommu_enable(dev->dev);
}
writel(iccl0, base + CIF_ICCL);
writel(clk_ctrl0, base + CTRL_VI_ISP_CLK_CTRL);
if (dev->is_unite) {
writel(iccl1, dev->base_next_addr + CIF_ICCL);
writel(clk_ctrl1, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
}
/* default config */
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
/* disable csi_rx interrupt */
writel(0, dev->base_addr + CIF_ISP_CSI0_CTRL0);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
} else if (dev->isp_ver == ISP_V32) {
/* disable down samplling default */
writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_MPDS_WR_CTRL);
writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_BPDS_WR_CTRL);
writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
writel(0x37, dev->base_addr + ISP32_MI_WR_WRAP_CTRL);
}
}
static void isp_config_clk(struct rkisp_hw_dev *dev, int on)
@@ -722,22 +753,6 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev)
rkisp_set_clk_rate(dev->clks[5], rate);
rkisp_soft_reset(dev, false);
isp_config_clk(dev, true);
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
/* disable csi_rx interrupt */
writel(0, dev->base_addr + CIF_ISP_CSI0_CTRL0);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
} else if (dev->isp_ver == ISP_V32) {
/* disable down samplling default */
writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_MPDS_WR_CTRL);
writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_BPDS_WR_CTRL);
writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
writel(0x37, dev->base_addr + ISP32_MI_WR_WRAP_CTRL);
}
return 0;
err:
for (--i; i >= 0; --i)

2
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -1935,7 +1935,6 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
"MI_CTRL:%x, ISP_CTRL:%x\n",
readl(base + CIF_MI_CTRL), readl(base + CIF_ISP_CTRL));
val = rkisp_read(dev, CTRL_VI_ISP_CLK_CTRL, true);
if (!in_interrupt()) {
/* normal case */
/* check the isp_clk before isp reset operation */
@@ -1949,7 +1948,6 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
}
rkisp_soft_reset(dev->hw_dev, false);
}
rkisp_write(dev, CTRL_VI_ISP_CLK_CTRL, val, true);
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
writel(0, base + CIF_ISP_CSI0_CSI2_RESETN);