From be56805ce4e590a642e9f14a8f662fbc66832b45 Mon Sep 17 00:00:00 2001 From: Joy Cho Date: Mon, 17 Jun 2019 14:51:49 +0900 Subject: [PATCH] media: hdmitx: Update hdmi hpll generation logic of custombuilt mode Change-Id: If4ab95d0c95ac49f4ce78801e1c2346e6301635e --- drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index 8009cef59933..e5b4b3b24972 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -1043,8 +1043,8 @@ next: p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10); pr_info("[N2][%s] vic == HDMI_CUSTOMBUILT, frac_freq %d\n", __func__, custom_timing->frac_freq); - /* check if hpll clk output is under (100*10)MHz */ - if (p_enc[j].hpll_clk_out < 1000000) { + /* check if hpll clk output is under (140*10)MHz */ + if (p_enc[j].hpll_clk_out < 1400000) { p_enc[j].hpll_clk_out *= 4; /* control od dividers */ p_enc[j].od1 = 4; @@ -1056,6 +1056,10 @@ next: p_enc[j].od2 = 1; p_enc[j].od3 = 2; } + + pr_info("[N2] hpll_clk_out %d, od1 %d, od2 %d, od3 %d\n", + p_enc[j].hpll_clk_out, + p_enc[j].od1, p_enc[j].od2, p_enc[j].od3); } hdmitx_set_cts_sys_clk(hdev);