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deintlace: PQ the set of DI_MTN_CTRL [2/2]

Browse Source 
PD#SWPL-14508

Problem:
HDMI480I/AV IN some issue you can see at the subtitle

Solution:
modify the DI_MTN_CTRL bit24/30 from vlsi(feijun),at the start of
field (1,2)you need set the bit24->0xf,bit30->0x1,after that
bit30->0x0

Verify:
verfy it on marconi

Change-Id: Iaf06f087811d189fe555e6802f90b7a96c33f393
Signed-off-by: qianqian.cai <qianqian.cai@amlogic.com>
This commit is contained in:
qianqian.cai
2019-10-16 19:38:59 +08:00
committed by Tao Zeng
parent 114854aac2
commit d5db1061c3
2 changed files with 9 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -3448,6 +3448,9 @@ static void pre_de_process(void)
}
di_pre_stru.field_count_for_cont++;
if (di_pre_stru.field_count_for_cont >= 5)
DI_Wr_reg_bits(DI_MTN_CTRL, 0, 30, 1);
di_txl_patch_prog(di_pre_stru.cur_prog_flag,
di_pre_stru.field_count_for_cont, mcpre_en);

9
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -141,6 +141,8 @@ static void ma_di_init(void)
/* mtn setting */
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
DI_Wr_reg_bits(DI_MTN_CTRL, 1, 0, 1);
DI_Wr_reg_bits(DI_MTN_CTRL, 1, 30, 1);
DI_Wr_reg_bits(DI_MTN_CTRL, 0xf, 24, 4);
DI_Wr(DI_MTN_1_CTRL1, 0x202015);
} else
DI_Wr(DI_MTN_1_CTRL1, 0xa0202015);
@@ -756,9 +758,10 @@ void enable_di_pre_aml(
/*
* enable&disable contwr txt
*/
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B))
RDMA_WR_BITS(DI_MTN_CTRL, madi_en?5:0, 29, 3);
else
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
RDMA_WR_BITS(DI_MTN_CTRL, madi_en, 29, 1);
RDMA_WR_BITS(DI_MTN_CTRL, madi_en, 31, 1);
} else
RDMA_WR_BITS(DI_MTN_1_CTRL1, madi_en?5:0, 29, 3);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {