From d5dd0267d5df988bf635c3b3fbadd02a5275d4e5 Mon Sep 17 00:00:00 2001 From: Luo Wei Date: Mon, 14 Dec 2020 14:46:29 +0800 Subject: [PATCH] arm64: dts: rockchip: add dts file for rk3566-evb5 Signed-off-by: Luo Wei Change-Id: I3eeb023b7ce622acd8ed151f0948489d5cd07ad8 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-evb5-lp4x-v10.dts | 7 + .../dts/rockchip/rk3566-evb5-lp4x-v10.dtsi | 318 ++++++++++++++++++ 3 files changed, 326 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index c0b04a198671..5777f76921ca 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-i2s-mic-array.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-pdm-mic-array.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb5-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dts new file mode 100644 index 000000000000..600fc3c39586 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3566-evb5-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi new file mode 100644 index 000000000000..08a8e828225a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" +#include "rk3566-evb.dtsi" + +/ { + model = "Rockchip RK3566 EVB5 LP4X V10 Board"; + compatible = "rockchip,rk3566-evb5-lp4x-v10", "rockchip,rk3568"; + + pcie20_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie20_3v3"; + regulator-min-microvolt = <0100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <0100000 0x0 + 3300000 0x1>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc3v3_vga: vcc3v3-vga { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_vga"; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&audiopwmout_diff { + status = "disabled"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "disabled"; +}; + +&dig_acodec { + status = "disabled"; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&audiopwm_loutp + &audiopwm_loutn + &audiopwm_routp + &audiopwm_routn + >; +}; + +/* + * mipi_dphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +/* + * mipi_dphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&edp { + hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&edp_phy { + status = "disabled"; +}; + +&edp_in_vp0 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus>; + + tx_delay = <0x59>; + rx_delay = <0x2e>; + + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&hdmi { + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&i2c5 { + status = "disabled"; +}; + +&i2s3_2ch { + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mipi_dphy0 { + status = "okay"; +}; + +&mipi_dphy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie20_3v3>; + status = "disabled"; +}; + +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + +&uart3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&uart7 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + status = "disabled"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd0 { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd1 { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +};