From d6f0e7b388e46a34dee8475050d9647e95468232 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Thu, 26 Jul 2018 16:18:40 +0800 Subject: [PATCH] ARM64: rockchip: rk3399 reorder codes in rk3399-cdn-dp Sync with upstream codes. Change-Id: Ic5306bdf16125e46892b5a85339afec67ad85482 Signed-off-by: Jianqun Xu --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 778233be1cd2..9d1b3904ef5e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -465,11 +465,11 @@ compatible = "rockchip,rk3399-cdn-dp"; reg = <0x0 0xfec00000 0x0 0x100000>; interrupts = ; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; clock-names = "core-clk", "pclk", "spdif", "grf"; - assigned-clocks = <&cru SCLK_DP_CORE>; - assigned-clock-rates = <100000000>; power-domains = <&power RK3399_PD_HDCP>; phys = <&tcphy0_dp>, <&tcphy1_dp>; resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,