From d741b100b4d1f0988c8c9ab1a12ecf8fd8a130a7 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Thu, 16 Jun 2022 18:17:49 +0800 Subject: [PATCH] clk: rockchip: avoid unintentional integer overflow in rockchip_rk3588_pll_recalc_rate() Fixes: 58c1fa2ef200 ("clk: rockchip: add pll type for RK3588") Signed-off-by: Jianqun Xu Change-Id: I840458595475e9e1bb6df74453829ea22dd2d729 --- drivers/clk/rockchip/clk-pll.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 315cbb73e3f0..47922e110ed6 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1329,6 +1329,8 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, return pll->scaling; rockchip_rk3588_pll_get_params(pll, &cur); + if (cur.p == 0) + return prate; rate64 *= cur.m; do_div(rate64, cur.p); @@ -1337,7 +1339,8 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, /* fractional mode */ u64 frac_rate64 = prate * cur.k; - postdiv = cur.p * 65536; + postdiv = cur.p; + postdiv *= 65536; do_div(frac_rate64, postdiv); rate64 += frac_rate64; }