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UPSTREAM: arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399

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The ACLK_VIO is a parent clock used by a several children,
its suggested clock rate is 400MHz. Right now it gets 400MHz
because it sources from CPLL(800M) and divides by 2 after reset.
It's good not to rely on default values like this, so let's
explicitly set it.
NOTE: it's expected that at least one board may override cru node and
set the CPLL to 1.6 GHz. On that board it will be very important to be
explicit about aclk-vio being 400 MHz.

Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 3f7f3b0fb4)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Conflicts:
	arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi

Change-Id: Iadd22356e399e8d9b3a1f2bec981f2b41d813f3c
This commit is contained in:
Shunqian Zheng
2018-03-12 09:50:48 +08:00
committed by Tao Huang
parent 394c4096b7
commit d7f331169b
2 changed files with 25 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
View File

@@ -515,6 +515,27 @@
cpu-supply = <&ppvar_bigcpu>;
};
&cru {
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
<50000000>, <800000000>,
<100000000>, <50000000>,
<400000000>;
};
&emmc_phy {
status = "okay";
};

6
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@@ -1487,7 +1487,8 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>;
assigned-clock-rates =
<400000000>, <200000000>,
<400000000>, <200000000>,
@@ -1498,7 +1499,8 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>;
<100000000>, <50000000>,
<400000000>;
};
grf: syscon@ff770000 {