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add rk3188 rga dst / add rga2 drivers

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This commit is contained in:
zsq
2014-03-01 16:17:04 +08:00
parent 53d5a0a18a
commit d801335b2f
20 changed files with 4948 additions and 355 deletions
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8
arch/arm/boot/dts/rk3188.dtsi
View File

@@ -407,6 +407,14 @@
pinctrl-0 = <&lcdc1_lcdc>;
pinctrl-1 = <&lcdc1_gpio>;
status = "disabled";
};
rga@10114000 {
compatible = "rockchip,rga";
reg = <0x10114000 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates6 10>, <&clk_gates6 11>;
clock-names = "hclk_rga", "aclk_rga";
status = "disabled";
};
adc: adc@2006c000 {

2
arch/arm/configs/rockchip_defconfig
View File

@@ -497,4 +497,6 @@ CONFIG_LSM_MMAP_MIN_ADDR=4096
CONFIG_SECURITY_SELINUX=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_ROCKCHIP_RGA=y
# CONFIG_ROCKCHIP_RGA2=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

1
drivers/video/rockchip/Kconfig
View File

@@ -65,4 +65,5 @@ source "drivers/video/rockchip/transmitter/Kconfig"
source "drivers/video/rockchip/hdmi/Kconfig"
source "drivers/video/rockchip/tve/Kconfig"
source "drivers/video/rockchip/rga/Kconfig"
source "drivers/video/rockchip/rga2/Kconfig"

3
drivers/video/rockchip/Makefile
View File

@@ -1,4 +1,5 @@
obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o lcdc/
obj-$(CONFIG_RK_TRSM) += transmitter/
obj-$(CONFIG_RGA_RK30) += rga/
obj-$(CONFIG_ROCKCHIP_RGA) += rga/
obj-$(CONFIG_ROCKCHIP_RGA2) += rga2/
obj-$(CONFIG_RK_HDMI) += display-sys.o hdmi/

6
drivers/video/rockchip/rga/Kconfig
View File

@@ -1,8 +1,8 @@
menu "RGA"
depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026
depends on ARCH_ROCKCHIP
config RGA_RK30
tristate "ROCKCHIP RK30 || RK2928 RGA"
config ROCKCHIP_RGA
tristate "ROCKCHIP_RGA"
help
rk30 rga module.

2
drivers/video/rockchip/rga/Makefile
View File

@@ -1,3 +1,3 @@
rga-y := rga_drv.o rga_mmu_info.o rga_reg_info.o RGA_API.o
obj-$(CONFIG_RGA_RK30) += rga.o
obj-$(CONFIG_ROCKCHIP_RGA) += rga.o

62
drivers/video/rockchip/rga/rga_drv.c
View File

@@ -27,8 +27,8 @@
#include <asm/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <mach/io.h>
#include <mach/irqs.h>
//#include <mach/io.h>
//#include <mach/irqs.h>
#include <linux/fs.h>
#include <asm/uaccess.h>
#include <linux/miscdevice.h>
@@ -89,9 +89,9 @@ struct rga_drvdata {
void (*rga_irq_callback)(int rga_retval); //callback function used by aync call
struct wake_lock wake_lock;
struct clk *pd_rga;
struct clk *aclk_rga;
struct clk *hclk_rga;
struct clk *pd_rga;
struct clk *hclk_rga;
};
static struct rga_drvdata *drvdata;
@@ -1122,9 +1122,18 @@ static struct miscdevice rga_dev ={
.fops = &rga_fops,
};
static int __devinit rga_drv_probe(struct platform_device *pdev)
static const struct of_device_id rockchip_rga_of_match[] = {
{ .compatible = "rockchip,rga", .data = NULL, },
{},
};
static int rga_drv_probe(struct platform_device *pdev)
{
struct rga_drvdata *data;
struct resource *res;
struct device_node *np = pdev->dev.of_node;
int ret = 0;
INIT_LIST_HEAD(&rga_service.waiting);
@@ -1138,9 +1147,8 @@ static int __devinit rga_drv_probe(struct platform_device *pdev)
rga_service.last_prc_src_format = 1; /* default is yuv first*/
rga_service.enable = false;
data = kzalloc(sizeof(struct rga_drvdata), GFP_KERNEL);
if(NULL == data)
{
data = devm_kzalloc(&pdev->dev, sizeof(struct rga_drvdata), GFP_KERNEL);
if(! data) {
ERR("failed to allocate driver data.\n");
return -ENOMEM;
}
@@ -1148,36 +1156,33 @@ static int __devinit rga_drv_probe(struct platform_device *pdev)
INIT_DELAYED_WORK(&data->power_off_work, rga_power_off_work);
wake_lock_init(&data->wake_lock, WAKE_LOCK_SUSPEND, "rga");
data->pd_rga = clk_get(NULL, "pd_rga");
data->aclk_rga = clk_get(NULL, "aclk_rga");
data->hclk_rga = clk_get(NULL, "hclk_rga");
//data->pd_rga = devm_clk_get(&pdev->dev, "pd_rga");
data->aclk_rga = devm_clk_get(&pdev->dev, "aclk_rga");
data->hclk_rga = devm_clk_get(&pdev->dev, "hclk_rga");
/* map the memory */
if (!request_mem_region(RK30_RGA_PHYS, RK30_RGA_SIZE, "rga_io"))
{
pr_info("failed to reserve rga HW regs\n");
return -EBUSY;
}
clk_prepare_enable(data->aclk_rga);
clk_prepare_enable(data->hclk_rga);
data->rga_base = (void*)ioremap_nocache(RK30_RGA_PHYS, RK30_RGA_SIZE);
if (data->rga_base == NULL)
{
/* map the registers */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->rga_base = devm_ioremap_resource(&pdev->dev, res);
if (!data->rga_base) {
ERR("rga ioremap failed\n");
ret = -ENOENT;
goto err_ioremap;
}
/* get the IRQ */
data->irq = platform_get_irq(pdev, 0);
if (data->irq <= 0)
{
data->irq = ret = platform_get_irq(pdev, 0);
if (ret <= 0) {
ERR("failed to get rga irq resource (%d).\n", data->irq);
ret = data->irq;
goto err_irq;
}
/* request the IRQ */
ret = request_threaded_irq(data->irq, rga_irq, rga_irq_thread, 0, "rga", pdev);
//ret = request_threaded_irq(data->irq, rga_irq, rga_irq_thread, 0, "rga", pdev);
ret = devm_request_threaded_irq(&pdev->dev, data->irq, rga_irq, rga_irq_thread, 0, "rga", data);
if (ret)
{
ERR("rga request_irq failed (%d).\n", ret);
@@ -1219,17 +1224,20 @@ static int rga_drv_remove(struct platform_device *pdev)
free_irq(data->irq, &data->miscdev);
iounmap((void __iomem *)(data->rga_base));
clk_put(data->pd_rga);
clk_disable_unprepare(data->aclk_rga);
clk_disable_unprepare(data->hclk_rga);
//clk_put(data->pd_rga);
clk_put(data->aclk_rga);
clk_put(data->hclk_rga);
kfree(data);
//kfree(data);
return 0;
}
static struct platform_driver rga_driver = {
.probe = rga_drv_probe,
.remove = __devexit_p(rga_drv_remove),
.remove = rga_drv_remove,
.driver = {
.owner = THIS_MODULE,
.name = "rga",

646
drivers/video/rockchip/rga/rga_reg_info.c
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File diff suppressed because it is too large Load Diff

9
drivers/video/rockchip/rga2/Kconfig Normal file
View File

@@ -0,0 +1,9 @@
menu "RGA2"
depends on ARCH_ROCKCHIP
config ROCKCHIP_RGA2
tristate "ROCKCHIP_RGA2"
help
rk32 rga2 module.
endmenu

3
drivers/video/rockchip/rga2/Makefile Normal file
View File

@@ -0,0 +1,3 @@
rga2-y := rga2_drv.o rga2_mmu_info.o rga2_reg_info.o RGA2_API.o
obj-$(CONFIG_ROCKCHIP_RGA2) += rga2.o

22
drivers/video/rockchip/rga2/RGA2_API.c Normal file
View File

@@ -0,0 +1,22 @@
#include <linux/memory.h>
#include "RGA2_API.h"
#include "rga2.h"
//#include "rga_angle.h"
#define IS_YUV_420(format) \
((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP))
#define IS_YUV_422(format) \
((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
#define IS_YUV(format) \
((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \
(format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))

12
drivers/video/rockchip/rga2/RGA2_API.h Normal file
View File

@@ -0,0 +1,12 @@
#ifndef __RGA_API_H__
#define __RGA_API_H__
#include "rga2_reg_info.h"
#include "rga2.h"
#define ENABLE 1
#define DISABLE 0
#endif

636
drivers/video/rockchip/rga2/rga2.h Normal file
View File

@@ -0,0 +1,636 @@
#ifndef _RGA_DRIVER_H_
#define _RGA_DRIVER_H_
#include <linux/mutex.h>
#define RGA_BLIT_SYNC 0x5017
#define RGA_BLIT_ASYNC 0x5018
#define RGA_FLUSH 0x5019
#define RGA_GET_RESULT 0x501a
#define RGA_GET_VERSION 0x501b
#define RGA2_BLIT_SYNC 0x6017
#define RGA2_BLIT_ASYNC 0x6018
#define RGA2_FLUSH 0x6019
#define RGA2_GET_RESULT 0x601a
#define RGA2_GET_VERSION 0x601b
#define RGA2_REG_CTRL_LEN 0x8 /* 8 */
#define RGA2_REG_CMD_LEN 0x20 /* 32 */
#define RGA2_CMD_BUF_SIZE 0x700 /* 16*28*4 */
#define RGA2_OUT_OF_RESOURCES -10
#define RGA2_MALLOC_ERROR -11
#define SCALE_DOWN_LARGE 1
#define rgaIS_ERROR(status) (status < 0)
#define rgaNO_ERROR(status) (status >= 0)
#define rgaIS_SUCCESS(status) (status == 0)
/* RGA2 process mode enum */
enum
{
bitblt_mode = 0x0,
color_palette_mode = 0x1,
color_fill_mode = 0x2,
update_palette_table_mode = 0x3,
update_patten_buff_mode = 0x4,
}; /*render mode*/
enum
{
A_B_B =0x0,
A_B_C =0x1,
}; //bitblt_mode select
enum
{
rop_enable_mask = 0x2,
dither_enable_mask = 0x8,
fading_enable_mask = 0x10,
PD_enbale_mask = 0x20,
};
/*
// Alpha Red Green Blue
{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
{ 2, 16, {{ 0, 0, 5, 0 11, 5, 16,11}}, GGL_BGR }, // RK_FORMAT_BGR_565
{ 2, 16, {{ 1, 0, 6, 1, 11, 6, 16,11}}, GGL_BGRA }, // RK_FORMAT_BGRA_5551
{ 2, 16, {{ 4, 0, 8, 4, 12, 8, 16,12}}, GGL_BGRA }, // RK_FORMAT_BGRA_4444
*/
enum
{
RGA2_FORMAT_RGBA_8888 = 0x0,
RGA2_FORMAT_RGBX_8888 = 0x1,
RGA2_FORMAT_RGB_888 = 0x2,
RGA2_FORMAT_BGRA_8888 = 0x3,
RGA2_FORMAT_BGRX_8888 = 0x4,
RGA2_FORMAT_BGR_888 = 0x5,
RGA2_FORMAT_RGB_565 = 0x6,
RGA2_FORMAT_RGBA_5551 = 0x7,
RGA2_FORMAT_RGBA_4444 = 0x8,
RGA2_FORMAT_BGR_565 = 0x9,
RGA2_FORMAT_BGRA_5551 = 0xa,
RGA2_FORMAT_BGRA_4444 = 0xb,
RGA2_FORMAT_YCbCr_422_SP = 0x10,
RGA2_FORMAT_YCbCr_422_P = 0x11,
RGA2_FORMAT_YCbCr_420_SP = 0x12,
RGA2_FORMAT_YCbCr_420_P = 0x13,
RGA2_FORMAT_YCrCb_422_SP = 0x14,
RGA2_FORMAT_YCrCb_422_P = 0x15,
RGA2_FORMAT_YCrCb_420_SP = 0x16,
RGA2_FORMAT_YCrCb_420_P = 0x17,
};
typedef struct mdp_img
{
u16 width;
u16 height;
u32 format;
u32 mem_addr;
}
mdp_img;
typedef struct mdp_img_act
{
u16 width; // width
u16 height; // height
s16 x_off; // x offset for the vir
s16 y_off; // y offset for the vir
s16 uv_x_off;
s16 uv_y_off;
}
mdp_img_act;
typedef struct mdp_img_vir
{
u16 width;
u16 height;
u32 format;
u32 mem_addr;
u32 uv_addr;
u32 v_addr;
}
mdp_img_vir;
typedef struct MMU_INFO
{
u32 src0_base_addr;
u32 src1_base_addr;
u32 dst_base_addr;
u32 els_base_addr;
u8 src0_mmu_flag; /* [0] src0 mmu enable [1] src0_flush [2] src0_prefetch_en [3] src0_prefetch dir */
u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch dir */
u8 dst_mmu_flag; /* [0] dst mmu enable [1] dst_flush [2] dst_prefetch_en [3] dst_prefetch dir */
u8 els_mmu_flag; /* [0] els mmu enable [1] els_flush [2] els_prefetch_en [3] els_prefetch dir */
} MMU_INFO;
enum
{
MMU_DIS = 0x0,
MMU_EN = 0x1
};
enum
{
MMU_FLUSH_DIS = 0x0,
MMU_FLUSH_EN = 0x2
};
enum
{
MMU_PRE_DIS = 0x0,
MMU_PRE_EN = 0x4
};
enum
{
MMU_PRE_DIR_FORW = 0x0,
MMU_PRE_DIR_BACK = 0x8
};
typedef struct COLOR_FILL
{
s16 gr_x_a;
s16 gr_y_a;
s16 gr_x_b;
s16 gr_y_b;
s16 gr_x_g;
s16 gr_y_g;
s16 gr_x_r;
s16 gr_y_r;
}
COLOR_FILL;
enum
{
ALPHA_ORIGINAL = 0x0,
ALPHA_NO_128 = 0x1
};
enum
{
R2_BLACK = 0x00,
R2_COPYPEN = 0xf0,
R2_MASKNOTPEN = 0x0a,
R2_MASKPEN = 0xa0,
R2_MASKPENNOT = 0x50,
R2_MERGENOTPEN = 0xaf,
R2_MERGEPEN = 0xfa,
R2_MERGEPENNOT = 0xf5,
R2_NOP = 0xaa,
R2_NOT = 0x55,
R2_NOTCOPYPEN = 0x0f,
R2_NOTMASKPEN = 0x5f,
R2_NOTMERGEPEN = 0x05,
R2_NOTXORPEN = 0xa5,
R2_WHITE = 0xff,
R2_XORPEN = 0x5a
};
/***************************************/
/* porting from rga.h for msg convert */
/***************************************/
typedef struct FADING
{
uint8_t b;
uint8_t g;
uint8_t r;
uint8_t res;
}
FADING;
typedef struct MMU
{
unsigned char mmu_en;
uint32_t base_addr;
uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
} MMU;
typedef struct RECT
{
unsigned short xmin;
unsigned short xmax; // width - 1
unsigned short ymin;
unsigned short ymax; // height - 1
} RECT;
typedef struct POINT
{
unsigned short x;
unsigned short y;
}
POINT;
typedef struct line_draw_t
{
POINT start_point; /* LineDraw_start_point */
POINT end_point; /* LineDraw_end_point */
uint32_t color; /* LineDraw_color */
uint32_t flag; /* (enum) LineDrawing mode sel */
uint32_t line_width; /* range 1~16 */
}
line_draw_t;
typedef struct rga_img_info_t
{
unsigned int yrgb_addr; /* yrgb mem addr */
unsigned int uv_addr; /* cb/cr mem addr */
unsigned int v_addr; /* cr mem addr */
unsigned int format; //definition by RK_FORMAT
unsigned short act_w;
unsigned short act_h;
unsigned short x_offset;
unsigned short y_offset;
unsigned short vir_w;
unsigned short vir_h;
unsigned short endian_mode; //for BPP
unsigned short alpha_swap;
//unsigned short uv_x_off;
//unsigned short uv_y_off;
}
rga_img_info_t;
struct rga_req {
uint8_t render_mode; /* (enum) process mode sel */
rga_img_info_t src; /* src image info */
rga_img_info_t dst; /* dst image info */
rga_img_info_t pat; /* patten image info */
uint32_t rop_mask_addr; /* rop4 mask addr */
uint32_t LUT_addr; /* LUT addr */
RECT clip; /* dst clip window default value is dst_vir */
/* value from [0, w-1] / [0, h-1]*/
int32_t sina; /* dst angle default value 0 16.16 scan from table */
int32_t cosa; /* dst angle default value 0 16.16 scan from table */
uint16_t alpha_rop_flag; /* alpha rop process flag */
/* ([0] = 1 alpha_rop_enable) */
/* ([1] = 1 rop enable) */
/* ([2] = 1 fading_enable) */
/* ([3] = 1 PD_enable) */
/* ([4] = 1 alpha cal_mode_sel) */
/* ([5] = 1 dither_enable) */
/* ([6] = 1 gradient fill mode sel) */
/* ([7] = 1 AA_enable) */
uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
uint32_t color_key_max; /* color key max */
uint32_t color_key_min; /* color key min */
uint32_t fg_color; /* foreground color */
uint32_t bg_color; /* background color */
COLOR_FILL gr_color; /* color fill use gradient */
line_draw_t line_draw_info;
FADING fading;
uint8_t PD_mode; /* porter duff alpha mode sel */
uint8_t alpha_global_value; /* global alpha value */
uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
uint8_t endian_mode; /* 0/big endian 1/little endian*/
uint8_t rotate_mode; /* (enum) rotate mode */
/* 0x0, no rotate */
/* 0x1, rotate */
/* 0x2, x_mirror */
/* 0x3, y_mirror */
uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
MMU mmu_info; /* mmu information */
uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
/* ([2~3] rop mode) */
/* ([4] zero mode en) */
/* ([5] dst alpha mode) */
/* ([6] alpha output mode sel) 0 src / 1 dst*/
uint8_t src_trans_mode;
};
struct rga2_req
{
u8 render_mode; /* (enum) process mode sel */
rga_img_info_t src; // src active window
rga_img_info_t src1; // src1 active window
rga_img_info_t dst; // dst active window
rga_img_info_t pat; // patten active window
u32 rop_mask_addr; // rop4 mask addr
u32 LUT_addr; // LUT addr
u32 rop_mask_stride;
u8 bitblt_mode; /* 0: SRC + DST => DST */
/* 1: SRC + SRC1 => DST */
u8 rotate_mode; /* [1:0] */
/* 0 degree 0x0 */
/* 90 degree 0x1 */
/* 180 degree 0x2 */
/* 270 degree 0x3 */
/* [5:4] */
/* none 0x0 */
/* x_mirror 0x1 */
/* y_mirror 0x2 */
/* x_mirror + y_mirror 0x3 */
u16 alpha_rop_flag; /* alpha rop process flag */
/* ([0] = 1 alpha_rop_enable) */
/* ([1] = 1 rop enable) */
/* ([2] = 1 fading_enable) */
/* ([3] = 1 alpha cal_mode_sel) */
/* ([4] = 1 src_dither_up_enable) */
/* ([5] = 1 dst_dither_up_enable) */
/* ([6] = 1 dither_down_enable) */
/* ([7] = 1 gradient fill mode sel) */
u16 alpha_mode_0; /* [0] SrcAlphaMode0 */
/* [2:1] SrcGlobalAlphaMode0 */
/* [3] SrcAlphaSelectMode0 */
/* [6:4] SrcFactorMode0 */
/* [7] SrcColorMode */
/* [8] DstAlphaMode0 */
/* [10:9] DstGlobalAlphaMode0 */
/* [11] DstAlphaSelectMode0 */
/* [14:12] DstFactorMode0 */
/* [15] DstColorMode0 */
u16 alpha_mode_1; /* [0] SrcAlphaMode1 */
/* [2:1] SrcGlobalAlphaMode1 */
/* [3] SrcAlphaSelectMode1 */
/* [6:4] SrcFactorMode1 */
/* [8] DstAlphaMode1 */
/* [10:9] DstGlobalAlphaMode1 */
/* [11] DstAlphaSelectMode1 */
/* [14:12] DstFactorMode1 */
u8 scale_bicu_mode; /* 0 1 2 3 */
u32 color_key_max; /* color key max */
u32 color_key_min; /* color key min */
u32 fg_color; /* foreground color */
u32 bg_color; /* background color */
u8 color_fill_mode;
COLOR_FILL gr_color; /* color fill use gradient */
u8 fading_alpha_value; /* Fading value */
u8 fading_r_value;
u8 fading_g_value;
u8 fading_b_value;
u8 src_a_global_val; /* src global alpha value */
u8 dst_a_global_val; /* dst global alpha value */
u8 rop_mode;
u16 rop_code; /* rop2/3/4 code */
u8 palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
u8 yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
u8 endian_mode; /* 0/little endian 1/big endian */
u8 CMD_fin_int_enable;
MMU_INFO mmu_info; /* mmu infomation */
u8 alpha_zero_key;
u8 src_trans_mode;
u8 alpha_swp;
u8 dither_mode;
u8 rgb2yuv_mode;
};
struct rga2_mmu_buf_t {
int32_t front;
int32_t back;
int32_t size;
int32_t curr;
unsigned int *buf;
unsigned int *buf_virtual;
};
//add for FPGA test ,by hxx & luj
enum
{
BB_ROTATE_OFF = 0x0, /* no rotate */
BB_ROTATE_90 = 0x1, /* rotate 90 */
BB_ROTATE_180 = 0x2, /* rotate 180 */
BB_ROTATE_270 = 0x3, /* rotate 270 */
}; /*rotate mode*/
enum
{
BB_MIRROR_OFF = (0x0 << 4), /* no mirror */
BB_MIRROR_X = (0x1 << 4), /* x mirror */
BB_MIRROR_Y = (0x2 << 4), /* y mirror */
BB_MIRROR_XY = (0x3 << 4), /* xy mirror */
}; /*mirror mode*/
enum
{
BB_COPY_USE_TILE = (0x1 << 6), /* bitblt mode copy but use Tile mode */
};
enum
{
//BYPASS = 0x0,
BT_601_RANGE0 = 0x1,
BT_601_RANGE1 = 0x2,
BT_709_RANGE0 = 0x3,
}; /*yuv2rgb_mode*/
enum
{
BPP1 = 0x0, /* BPP1 */
BPP2 = 0x1, /* BPP2 */
BPP4 = 0x2, /* BPP4 */
BPP8 = 0x3 /* BPP8 */
}; /*palette_mode*/
enum
{
SOLID_COLOR = 0x0, //color fill mode; ROP4: SOLID_rop4_mask_addr COLOR
PATTERN_COLOR = 0x1 //pattern_fill_mode;ROP4:PATTERN_COLOR
}; /*color fill mode*/
enum
{
COLOR_FILL_CLIP = 0x0,
COLOR_FILL_NOT_CLIP = 0x1
};
enum
{
CATROM = 0x0,
MITCHELL = 0x1,
HERMITE = 0x2,
B_SPLINE = 0x3,
}; /*bicubic coefficient*/
enum
{
ROP2 = 0x0,
ROP3 = 0x1,
ROP4 = 0x2
}; /*ROP mode*/
enum
{
BIG_ENDIAN = 0x0,
LITTLE_ENDIAN = 0x1
}; /*endian mode*/
enum
{
MMU_TABLE_4KB = 0x0,
MMU_TABLE_64KB = 0x1,
}; /*MMU table size*/
enum
{
RGB_2_666 = 0x0,
RGB_2_565 = 0x1,
RGB_2_555 = 0x2,
RGB_2_444 = 0x3,
}; /*dither down mode*/
/**
* struct for process session which connect to rga
*
* @author ZhangShengqin (2012-2-15)
*/
typedef struct rga2_session {
/* a linked list of data so we can access them for debugging */
struct list_head list_session;
/* a linked list of register data waiting for process */
struct list_head waiting;
/* a linked list of register data in processing */
struct list_head running;
/* all coommand this thread done */
atomic_t done;
wait_queue_head_t wait;
pid_t pid;
atomic_t task_running;
atomic_t num_done;
} rga2_session;
struct rga2_reg {
rga2_session *session;
struct list_head session_link; /* link to rga service session */
struct list_head status_link; /* link to register set list */
uint32_t sys_reg[8];
uint32_t cmd_reg[32];
uint32_t *MMU_base;
uint32_t MMU_len;
//atomic_t int_enable;
//struct rga_req req;
};
struct rga2_service_info {
struct mutex lock;
struct timer_list timer; /* timer for power off */
struct list_head waiting; /* link to link_reg in struct vpu_reg */
struct list_head running; /* link to link_reg in struct vpu_reg */
struct list_head done; /* link to link_reg in struct vpu_reg */
struct list_head session; /* link to list_session in struct vpu_session */
atomic_t total_running;
struct rga2_reg *reg;
uint32_t cmd_buff[32*8];/* cmd_buff for rga */
uint32_t *pre_scale_buf;
atomic_t int_disable; /* 0 int enable 1 int disable */
atomic_t cmd_num;
atomic_t src_format_swt;
int last_prc_src_format;
atomic_t rga_working;
bool enable;
//struct rga_req req[10];
struct mutex mutex; // mutex
};
#define RGA2_TEST_CASE 0
#define RGA2_TEST 0
#define RGA2_TEST_MSG 0
#define RGA2_TEST_TIME 0
#if defined(CONFIG_ARCH_RK3190)
#define RGA2_BASE 0x1010c000
#elif defined(CONFIG_ARCH_RK32)
#define RGA2_BASE 0x10114000
#endif
//General Registers
#define RGA2_SYS_CTRL 0x000
#define RGA2_CMD_CTRL 0x004
#define RGA2_CMD_BASE 0x008
#define RGA2_STATUS 0x00c
#define RGA2_INT 0x010
#define RGA2_MMU_CTRL0 0x018
#define RGA2_MMU_CMD_BASE 0x01c
//Command code start
#define RGA2_MODE_CTRL 0x100
#define RGA_BLIT_COMPLETE_EVENT 1
long rga2_ioctl_kernel(struct rga2_req *req);
#endif /*_RK29_IPP_DRIVER_H_*/

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drivers/video/rockchip/rga2/rga2_mmu_info.c Normal file
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#ifndef __RGA_MMU_INFO_H__
#define __RGA_MMU_INFO_H__
#include "rga2.h"
#ifndef MIN
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
#endif
#ifndef MAX
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
#endif
int rga2_set_mmu_info(struct rga2_reg *reg, struct rga2_req *req);
#endif

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#ifndef __REG2_INFO_H__
#define __REG2_INFO_H__
//#include "chip_register.h"
//#include "rga_struct.h"
#include "rga2.h"
#ifndef MIN
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
#endif
#ifndef MAX
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
#endif
#ifndef ABS
#define ABS(X) (((X) < 0) ? (-(X)) : (X))
#endif
#ifndef CLIP
#define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
#endif
#define rRGA_SYS_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_SYS_CTRL_OFFSET ))
#define rRGA_CMD_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_CTRL_OFFSET ))
#define rRGA_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_BASE_OFFSET ))
#define rRGA_STATUS (*(volatile u32 *)(RGA2_BASE + RGA2_STATUS_OFFSET ))
#define rRGA_INT (*(volatile u32 *)(RGA2_BASE + RGA2_INT_OFFSET ))
#define rRGA_MMU_CTRL0 (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CTRL0_OFFSET ))
#define rRGA_MMU_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CMD_BASE_OFFSET))
#define rRGA_CMD_ADDR (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_ADDR))
/*RGA_INT*/
#define m_RGA2_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )
#define m_RGA2_INT_MMU_INT_EN ( 1<<9 )
#define m_RGA2_INT_ERROR_INT_EN ( 1<<8 )
#define m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )
#define m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )
#define m_RGA2_INT_MMU_INT_CLEAR ( 1<<5 )
#define m_RGA2_INT_ERROR_INT_CLEAR ( 1<<4 )
#define m_RGA2_INT_CUR_CMD_DONE_INT_FLAG ( 1<<3 )
#define m_RGA2_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )
#define m_RGA2_INT_MMU_INT_FLAG ( 1<<1 )
#define m_RGA2_INT_ERROR_INT_FLAG ( 1<<0 )
#define s_RGA2_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )
#define s_RGA2_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )
#define s_RGA2_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )
#define s_RGA2_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )
#define s_RGA2_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )
#define s_RGA2_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )
#define s_RGA2_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )
/* RGA_MODE_CTRL */
#define m_RGA2_MODE_CTRL_SW_RENDER_MODE ( 0x7<<0 )
#define m_RGA2_MODE_CTRL_SW_BITBLT_MODE ( 0x1<<3 )
#define m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT ( 0x1<<4 )
#define m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET ( 0x1<<5 )
#define m_RGA2_MODE_CTRL_SW_GRADIENT_SAT ( 0x1<<6 )
#define m_RGA2_MODE_CTRL_SW_INTR_CF_E ( 0x1<<7 )
#define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x) ( (x&0x7)<<0 )
#define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x) ( (x&0x1)<<3 )
#define s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(x) ( (x&0x1)<<4 )
#define s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(x) ( (x&0x1)<<5 )
#define s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(x) ( (x&0x1)<<6 )
#define s_RGA2_MODE_CTRL_SW_INTR_CF_E(x) ( (x&0x1)<<7 )
/* RGA_SRC_INFO */
#define m_RGA2_SRC_INFO_SW_SRC_FMT ( 0xf<<0 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP ( 0x1<<4 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP ( 0x1<<5 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP ( 0x1<<6 )
#define m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN ( 0x1<<7 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE ( 0x3<<8 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE ( 0x3<<10 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE ( 0x3<<12 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE ( 0x3<<14 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE ( 0x3<<16 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE ( 0x1<<18 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E ( 0xf<<19 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E ( 0x1<<23 )
#define m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER ( 0x3<<24 )
#define m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL ( 0x1<<26 )
#define s_RGA2_SRC_INFO_SW_SRC_FMT(x) ( (x&0xf)<<0 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(x) ( (x&0x1)<<4 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(x) ( (x&0x1)<<5 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(x) ( (x&0x1)<<6 )
#define s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(x) ( (x&0x1)<<7 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(x) ( (x&0x3)<<8 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(x) ( (x&0x3)<<10 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE(x) ( (x&0x3)<<12 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x) ( (x&0x3)<<14 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(x) ( (x&0x3)<<16 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(x) ( (x&0x1)<<18 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(x) ( (x&0xf)<<19 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E(x) ( (x&0x1)<<23 )
#define s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER(x) ( (x&0x3)<<24 )
#define s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL(x) ( (x&0x1)<<26 )
/* RGA_SRC_VIR_INFO */
#define m_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE ( 0x7fff<<0 ) //modify
#define m_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE ( 0x3ff<<16 ) //modify
#define s_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE(x) ( (x&0x7fff)<<0 ) //modify
#define s_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE(x) ( (x&0x3ff)<<16 ) //modify
/* RGA_SRC_ACT_INFO */
#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH ( 0x1fff<<0 )
#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT ( 0x1fff<<16 )
#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ( (x&0x1fff)<<0 )
#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ( (x&0x1fff<)<16 )
/* RGA_DST_INFO */
#define m_RGA2_DST_INFO_SW_DST_FMT ( 0xf<<0 )
#define m_RGA2_DST_INFO_SW_DST_RB_SWAP ( 0x1<<4 )
#define m_RGA2_DST_INFO_SW_ALPHA_SWAP ( 0x1<<5 )
#define m_RGA2_DST_INFO_SW_DST_UV_SWAP ( 0x1<<6 )
#define m_RGA2_DST_INFO_SW_SRC1_FMT ( 0x7<<7 )
#define m_RGA2_DST_INFO_SW_SRC1_RB_SWP ( 0x1<<10)
#define m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP ( 0x1<<11)
#define m_RGA2_DST_INFO_SW_DITHER_UP_E ( 0x1<<12)
#define m_RGA2_DST_INFO_SW_DITHER_DOWN_E ( 0x1<<13)
#define m_RGA2_DST_INFO_SW_DITHER_MODE ( 0x3<<14)
#define m_RGA2_DST_INFO_SW_DST_CSC_MODE ( 0x3<<16) //add
#define m_RGA2_DST_INFO_SW_CSC_CLIP_MODE ( 0x1<<18)
#define s_RGA2_DST_INFO_SW_DST_FMT(x) ( (x&0xf)<<0 )
#define s_RGA2_DST_INFO_SW_DST_RB_SWAP(x) ( (x&0x1)<<4 )
#define s_RGA2_DST_INFO_SW_ALPHA_SWAP(x) ( (x&0x1)<<5 )
#define s_RGA2_DST_INFO_SW_DST_UV_SWAP(x) ( (x&0x1)<<6 )
#define s_RGA2_DST_INFO_SW_SRC1_FMT(x) ( (x&0x7)<<7 )
#define s_RGA2_DST_INFO_SW_SRC1_RB_SWP(x) ( (x&0x1)<<10)
#define s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(x) ( (x&0x1)<<11)
#define s_RGA2_DST_INFO_SW_DITHER_UP_E(x) ( (x&0x1)<<12)
#define s_RGA2_DST_INFO_SW_DITHER_DOWN_E(x) ( (x&0x1)<<13)
#define s_RGA2_DST_INFO_SW_DITHER_MODE(x) ( (x&0x3)<<14)
#define s_RGA2_DST_INFO_SW_DST_CSC_MODE(x) ( (x&0x3)<<16) //add
#define s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(x) ( (x&0x1)<<18)
/* RGA_ALPHA_CTRL0 */
#define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0 ( 0x1<<0 )
#define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL ( 0x1<<1 )
#define m_RGA2_ALPHA_CTRL0_SW_ROP_MODE ( 0x3<<2 )
#define m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA ( 0xff<<4 )
#define m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA ( 0xff<<12 )
#define m_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN ( 0x1<<20 ) //add
#define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(x) ( (x&0x1)<<0 )
#define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(x) ( (x&0x1)<<1 )
#define s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(x) ( (x&0x3)<<2 )
#define s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(x) ( (x&0xff)<<4 )
#define s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(x) ( (x&0xff)<<12 )
#define s_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN(x) ( (x&0x1)<<20 ) //add
/* RGA_ALPHA_CTRL1 */
#define m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0 ( 0x1<<0 )
#define m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0 ( 0x1<<1 )
#define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0 ( 0x7<<2 )
#define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0 ( 0x7<<5 )
#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0 ( 0x1<<8 )
#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0 ( 0x1<<9 )
#define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 ( 0x3<<10)
#define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0 ( 0x3<<12)
#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0 ( 0x1<<14)
#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0 ( 0x1<<15)
#define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1 ( 0x7<<16)
#define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1 ( 0x7<<19)
#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1 ( 0x1<<22)
#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1 ( 0x1<<23)
#define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1 ( 0x3<<24)
#define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1 ( 0x3<<26)
#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1 ( 0x1<<28)
#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1 ( 0x1<<29)
#define s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(x) ( (x&0x1)<<0 )
#define s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(x) ( (x&0x1)<<1 )
#define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(x) ( (x&0x7)<<2 )
#define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(x) ( (x&0x7)<<5 )
#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(x) ( (x&0x1)<<8 )
#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(x) ( (x&0x1)<<9 )
#define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ( (x&0x3)<<10)
#define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(x) ( (x&0x3)<<12)
#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(x) ( (x&0x1)<<14)
#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(x) ( (x&0x1)<<15)
#define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(x) ( (x&0x7)<<16)
#define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(x) ( (x&0x7)<<19)
#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(x) ( (x&0x1)<<22)
#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(x) ( (x&0x1)<<23)
#define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(x) ( (x&0x3)<<24)
#define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(x) ( (x&0x3)<<26)
#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(x) ( (x&0x1)<<28)
#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(x) ( (x&0x1)<<29)
/* RGA_MMU_CTRL1 */
#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_EN ( 0x1<<0 )
#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH ( 0x1<<1 )
#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN ( 0x1<<2 )
#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR ( 0x1<<3 )
#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN ( 0x1<<4 )
#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH ( 0x1<<5 )
#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN ( 0x1<<6 )
#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR ( 0x1<<7 )
#define m_RGA2_MMU_CTRL1_SW_DST_MMU_EN ( 0x1<<8 )
#define m_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH ( 0x1<<9 )
#define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN ( 0x1<<10 )
#define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR ( 0x1<<11 )
#define m_RGA2_MMU_CTRL1_SW_ELS_MMU_EN ( 0x1<<12 )
#define m_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH ( 0x1<<13 )
#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_EN(x) ( (x&0x1)<<0 )
#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH(x) ( (x&0x1)<<1 )
#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN(x) ( (x&0x1)<<2 )
#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR(x) ( (x&0x1)<<3 )
#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN(x) ( (x&0x1)<<4 )
#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH(x) ( (x&0x1)<<5 )
#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN(x) ( (x&0x1)<<6 )
#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR(x) ( (x&0x1)<<7 )
#define s_RGA2_MMU_CTRL1_SW_DST_MMU_EN(x) ( (x&0x1)<<8 )
#define s_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH(x) ( (x&0x1)<<9 )
#define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN(x) ( (x&0x1)<<10 )
#define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR(x) ( (x&0x1)<<11 )
#define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ( (x&0x1)<<12 )
#define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ( (x&0x1)<<13 )
#define RGA2_SYS_CTRL_OFFSET 0x0
#define RGA2_CMD_CTRL_OFFSET 0x4
#define RGA2_CMD_BASE_OFFSET 0x8
#define RGA2_STATUS_OFFSET 0xc
#define RGA2_INT_OFFSET 0x10
#define RGA2_MMU_CTRL0_OFFSET 0x14
#define RGA2_MMU_CMD_BASE_OFFSET 0x18
#define RGA2_MODE_CTRL_OFFSET 0x00
#define RGA2_SRC_INFO_OFFSET 0x04
#define RGA2_SRC_BASE0_OFFSET 0x08
#define RGA2_SRC_BASE1_OFFSET 0x0c
#define RGA2_SRC_BASE2_OFFSET 0x10
#define RGA2_SRC_BASE3_OFFSET 0x14
#define RGA2_SRC_VIR_INFO_OFFSET 0x18
#define RGA2_SRC_ACT_INFO_OFFSET 0x1c
#define RGA2_SRC_X_FACTOR_OFFSET 0x20
#define RGA2_SRC_Y_FACTOR_OFFSET 0x24
#define RGA2_SRC_BG_COLOR_OFFSET 0x28
#define RGA2_SRC_FG_COLOR_OFFSET 0x2c
#define RGA2_SRC_TR_COLOR0_OFFSET 0x30
#define RGA2_CF_GR_A_OFFSET 0x30 // repeat
#define RGA2_SRC_TR_COLOR1_OFFSET 0x34
#define RGA2_CF_GR_B_OFFSET 0x34 // repeat
#define RGA2_DST_INFO_OFFSET 0x38
#define RGA2_DST_BASE0_OFFSET 0x3c
#define RGA2_DST_BASE1_OFFSET 0x40
#define RGA2_DST_BASE2_OFFSET 0x44
#define RGA2_DST_VIR_INFO_OFFSET 0x48
#define RGA2_DST_ACT_INFO_OFFSET 0x4c
#define RGA2_ALPHA_CTRL0_OFFSET 0x50
#define RGA2_ALPHA_CTRL1_OFFSET 0x54
#define RGA2_FADING_CTRL_OFFSET 0x58
#define RGA2_PAT_CON_OFFSET 0x5c
#define RGA2_ROP_CTRL0_OFFSET 0x60
#define RGA2_CF_GR_G_OFFSET 0x60 // repeat
#define RGA2_ROP_CTRL1_OFFSET 0x64
#define RGA2_CF_GR_R_OFFSET 0x64 // repeat
#define RGA2_MASK_BASE_OFFSET 0x68
#define RGA2_MMU_CTRL1_OFFSET 0x6c
#define RGA2_MMU_SRC_BASE_OFFSET 0x70
#define RGA2_MMU_SRC1_BASE_OFFSET 0x74
#define RGA2_MMU_DST_BASE_OFFSET 0x78
#define RGA2_MMU_ELS_BASE_OFFSET 0x7c
int RGA2_gen_reg_info(unsigned char *base, struct rga2_req *msg);
void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req);
#endif

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drivers/video/rockchip/rga2/rga2_rop.h Normal file
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#ifndef __RGA_ROP_H__
#define __RGA_ROP_H__
#include "rga2_type.h"
UWORD32 ROP3_code[256] =
{
0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,
0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,
0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
};
#endif

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drivers/video/rockchip/rga2/rga2_type.h Normal file
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#ifndef __RGA_TYPE_H__
#define __RGA_TYPE_H__
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
typedef unsigned int UWORD32;
typedef unsigned int uint32;
typedef unsigned int RK_U32;
typedef unsigned short UWORD16;
typedef unsigned short RK_U16;
typedef unsigned char UBYTE;
typedef unsigned char RK_U8;
typedef int WORD32;
typedef int RK_S32;
typedef short WORD16;
typedef short RK_S16;
typedef char BYTE;
typedef char RK_S8;
#ifndef NULL
#define NULL 0L
#endif
#ifndef TRUE
#define TRUE 1L
#endif
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __RGA_TYPR_H__ */