diff --git a/arch/arm/boot/dts/rk3036-clocks.dtsi b/arch/arm/boot/dts/rk3036-clocks.dtsi deleted file mode 100755 index b692f309d312..000000000000 --- a/arch/arm/boot/dts/rk3036-clocks.dtsi +++ /dev/null @@ -1,1521 +0,0 @@ -/* - * Copyright (C) 2014 ROCKCHIP, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include - -/{ - - clocks { - compatible = "rockchip,rk-clocks"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000000 0x1f0>; - - fixed_rate_cons { - compatible = "rockchip,rk-fixed-rate-cons"; - - xin24m: xin24m { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "xin24m"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - xin12m: xin12m { - compatible = "rockchip,rk-fixed-clock"; - clocks = <&xin24m>; - clock-output-names = "xin12m"; - clock-frequency = <12000000>; - #clock-cells = <0>; - }; - - rmii_clkin: rmii_clkin { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "rmii_clkin"; - clock-frequency = <50000000>; - #clock-cells = <0>; - }; - - usb_480m: usb_480m { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "usb_480m"; - clock-frequency = <480000000>; - #clock-cells = <0>; - }; - - i2s_clkin: i2s_clkin { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "i2s_clkin"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - jtag_tck: jtag_tck { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "jtag_tck"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy: dummy { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "dummy"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy_cpll: dummy_cpll { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "dummy_cpll"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - }; - - fixed_factor_cons { - compatible = "rockchip,rk-fixed-factor-cons"; -/* - otgphy0_12m: otgphy0_12m { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_gates1 5>; - clock-output-names = "otgphy0_12m"; - clock-div = <1>; - clock-mult = <20>; - #clock-cells = <0>; - }; -*/ - hclk_vcodec: hclk_vcodec { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&aclk_vcodec_pre>; - clock-output-names = "hclk_vcodec"; - clock-div = <4>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - io_mac_mdclkout: io_mac_mdclkout { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&aclk_peri_pre>; - clock-output-names = "io_mac_mdclkout"; - clock-div = <2>; - clock-mult = <1>; - #clock-cells = <0>; - }; - }; - - clock_regs { - compatible = "rockchip,rk-clock-regs"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0000 0x01f0>; - ranges; - - /* PLL control regs */ - pll_cons { - compatible = "rockchip,rk-pll-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges ; - - clk_apll: pll-clk@0000 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0000 0x10>; - mode-reg = <0x0040 0>; - status-reg = <0x0004 10>; - clocks = <&xin24m>; - clock-output-names = "clk_apll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - clk_dpll: pll-clk@0010 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0010 0x10>; - mode-reg = <0x0040 4>; - status-reg = <0x0014 10>; - clocks = <&xin24m>; - clock-output-names = "clk_dpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - clk_gpll: pll-clk@0030 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0030 0x10>; - mode-reg = <0x0040 12>; - status-reg = <0x0034 10>; - clocks = <&xin24m>; - clock-output-names = "clk_gpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - /* Select control regs */ - clk_sel_cons { - compatible = "rockchip,rk-sel-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_sel_con0: sel-con@0044 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0044 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_core_div: clk_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_core>; - clock-output-names = "clk_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - }; - - /* reg[6:5]: reserved */ - - clk_core: clk_core_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&clk_apll>, <&clk_gates0 6>; - clock-output-names = "clk_core"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_cpu_pre_div: aclk_cpu_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_cpu_pre>; - clock-output-names = "aclk_cpu_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[13]: reserved */ - - aclk_cpu_pre: aclk_cpu_pre_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>; - clock-output-names = "aclk_cpu_pre"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con1: sel-con@0048 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0048 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - pclk_dbg_div: pclk_dbg_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 4>; - clocks = <&clk_core>; - clock-output-names = "pclk_dbg"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_core_pre: aclk_core_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <4 3>; - clocks = <&clk_core>; - clock-output-names = "aclk_core_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* reg[7]: reserved */ - - hclk_cpu_pre: hclk_cpu_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_cpu_pre>; - clock-output-names = "hclk_cpu_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[11:10]: reserved */ - - pclk_cpu_pre: pclk_cpu_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 3>; - clocks = <&aclk_cpu_pre>; - clock-output-names = "pclk_cpu_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15]: reserved */ - }; - - clk_sel_con2: sel-con@004c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x004c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - /* reg[3:0]: reserved */ - - clk_timer0: clk_timer0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <4 1>; - clocks = <&xin24m>, <&aclk_peri_pre>; - clock-output-names = "clk_timer0"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_timer1: clk_timer1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 1>; - clocks = <&xin24m>, <&aclk_peri_pre>; - clock-output-names = "clk_timer1"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_timer2: clk_timer2_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 1>; - clocks = <&xin24m>, <&aclk_peri_pre>; - clock-output-names = "clk_timer2"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_timer3: clk_timer3_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&xin24m>, <&aclk_peri_pre>; - clock-output-names = "clk_timer3"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15:8]: reserved */ - }; - - clk_sel_con3: sel-con@0050 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0050 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_i2s_pll_div: clk_i2s_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_i2s_pll>; - clock-output-names = "clk_i2s_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[7]: reserved */ - - clk_i2s: clk_i2s_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>; - clock-output-names = "clk_i2s"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[11:10]: reserved */ - - clk_i2s_out: i2s_outclk_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 1>; - clocks = <&xin12m>, <&clk_i2s>; - clock-output-names = "i2s_clkout"; - #clock-cells = <0>; - }; - - /* reg[13]: reserved */ - - clk_i2s_pll: i2s_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>; - clock-output-names = "clk_i2s_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con5: sel-con@0058 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0058 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_div: spdif_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spdif_pll>; - clock-output-names = "clk_spdif_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[7]: reserved */ - - clk_spdif: spdif_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>; - clock-output-names = "clk_spdif"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - clk_spdif_pll: spdif_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <10 2>; - clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>; - clock-output-names = "clk_spdif_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15:12]: reserved */ - }; - - clk_sel_con7: sel-con@0060 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0060 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - i2s_frac: i2s_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_i2s_pll>; - clock-output-names = "i2s_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con9: sel-con@0068 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0068 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_frac: spdif_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&spdif_div>; - clock-output-names = "spdif_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con10: sel-con@006c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x006c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_peri_pre_div: aclk_peri_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_peri_pre>; - clock-output-names = "aclk_peri_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[7:5]: reserved */ - - hclk_peri_pre: hclk_peri_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_peri_pre>; - clock-output-names = "hclk_peri_pre"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x2 4>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[11:10]: reserved */ - - pclk_peri_pre: pclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 2>; - clocks = <&aclk_peri_pre>; - clock-output-names = "pclk_peri_pre"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x2 4 - 0x3 8>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_peri_pre: aclk_peri_pre_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>; - clock-output-names = "aclk_peri_pre"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con11: sel-con@0070 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sdmmc0_div: clk_sdmmc0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&clk_sdmmc0>; - clock-output-names = "clk_sdmmc0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[7]: reserved */ - - clk_sdio_div: clk_sdio_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 7>; - clocks = <&clk_sdio>; - clock-output-names = "clk_sdio"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[15]: reserved */ - - }; - - clk_sel_con12: sel-con@0074 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_emmc_div: clk_emmc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_emmc>; - clock-output-names = "clk_emmc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[7]: reserved */ - - clk_sdmmc0: clk_sdmmc0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_sdmmc0"; - #clock-cells = <0>; - }; - - clk_sdio: clk_sdio_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <10 2>; - clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_sdio"; - #clock-cells = <0>; - }; - - clk_emmc: clk_emmc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 2>; - clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_emmc"; - #clock-cells = <0>; - }; - - /* reg[15:14]: reserved */ - }; - - clk_sel_con13: sel-con@0078 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart0_div: clk_uart0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart_pll>; - clock-output-names = "clk_uart0_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart0: clk_uart0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>; - clock-output-names = "clk_uart0"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - clk_uart_pll: clk_uart_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <10 2>; - clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>; - clock-output-names = "clk_uart_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15:12]: reserved */ - - }; - - clk_sel_con14: sel-con@007c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x007c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart1_div: clk_uart1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart_pll>; - clock-output-names = "clk_uart1_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart1: clk_uart1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>; - clock-output-names = "clk_uart1"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[15:10]: reserved */ - }; - - clk_sel_con15: sel-con@0080 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0080 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart2_div: clk_uart2_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart_pll>; - clock-output-names = "clk_uart2_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart2: clk_uart2_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>; - clock-output-names = "clk_uart2"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[15:10]: reserved */ - }; - - clk_sel_con16: sel-con@0084 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0084 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sfc: clk_sfc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_sfc"; - #clock-cells = <0>; - }; - - clk_sfc_div: clk_sfc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <2 5>; - clocks = <&clk_sfc>; - clock-output-names = "clk_sfc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[7]: reserved */ - - clk_nandc: clk_nandc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>; - clock-output-names = "clk_nandc"; - #clock-cells = <0>; - }; - - clk_nandc_div: clk_nandc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <10 5>; - clocks = <&clk_nandc>; - clock-output-names = "clk_nandc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[31:15]: reserved */ - }; - - clk_sel_con17: sel-con@0088 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0088 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart0_frac: uart0_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart0_div>; - clock-output-names = "uart0_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con18: sel-con@008c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x008c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart1_frac: uart1_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart1_div>; - clock-output-names = "uart1_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con19: sel-con@0090 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0090 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart2_frac: uart2_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart2_div>; - clock-output-names = "uart2_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con20: sel-con@0094 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0094 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_hevc_core: clk_hevc_core_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>; - clock-output-names = "clk_hevc_core"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_hevc_core_div: clk_hevc_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <2 5>; - clocks = <&clk_hevc_core>; - clock-output-names = "clk_hevc_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[31:7]: reserved */ - - }; - - clk_sel_con21: sel-con@0098 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0098 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_mac_pll: clk_mac_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>; - clock-output-names = "clk_mac_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[2]: reserved */ - - clk_mac_ref: clk_mac_ref_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <3 1>; - clocks = <&clk_mac_pll_div>, <&rmii_clkin>; - clock-output-names = "clk_mac_ref"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - #clock-init-cells = <1>; - }; - - clk_mac_ref_div: clk_mac_ref_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <4 5>; - clocks = <&clk_mac_ref>; - clock-output-names = "clk_mac"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_mac_pll_div: clk_mac_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <9 5>; - clocks = <&clk_mac_pll>; - clock-output-names = "clk_mac_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - #clock-init-cells = <1>; - }; - - /* reg[15:14]: reserved */ - }; - - clk_sel_con25: sel-con@00a8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_spi0_div: clk_spi0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spi0>; - clock-output-names = "clk_spi0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[7]: reserved */ - - clk_spi0: clk_spi0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>; - clock-output-names = "clk_spi0"; - #clock-cells = <0>; - }; - - /* reg[15:10]: reserved */ - - }; - - clk_sel_con26: sel-con@00ac { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00ac 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - ddr_div: ddr_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 2>; - clocks = <&clk_ddr>; - clock-output-names = "clk_ddr"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x3 4>; - #clock-cells = <0>; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - rockchip,clkops-idx = ; - }; - - /* reg[7:1]: reserved */ - - clk_ddr: ddr_clk_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 1>; - clocks = <&clk_dpll>, <&dummy>; - clock-output-names = "clk_ddr"; - #clock-cells = <0>; - }; - - /* reg[15:9]: reserved */ - }; - - clk_sel_con28: sel-con@00b4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - dclk_lcdc1: dclk_lcdc1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>; - clock-output-names = "dclk_lcdc1"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[7:2]: reserved */ - - dclk_lcdc1_div: dclk_lcdc1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&dclk_lcdc1>; - clock-output-names = "dclk_lcdc1"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - }; - - clk_sel_con30: sel-con@00bc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00bc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_testout_div: clk_testout_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&dummy>; - clock-output-names = "clk_testout"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[7:5]: reserved */ - - hclk_vio_pre_div: hclk_vio_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&hclk_vio_pre>; - clock-output-names = "hclk_vio_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[13]: reserved */ - - hclk_vio_pre: hclk_vio_pre_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>; - clock-output-names = "hclk_vio_pre"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con31: sel-con@00c0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_hdmi: clk_hdmi_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&dclk_lcdc1_div>, <&dummy>; - clock-output-names = "clk_hdmi"; - #clock-cells = <0>; - }; - - /* reg[7:1]: reserved */ - - aclk_vio_pre_div: aclk_vio_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_vio_pre>; - clock-output-names = "aclk_vio_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[13]: reserved */ - - aclk_vio_pre: aclk_vio_pre_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>; - clock-output-names = "aclk_vio_pre"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con32: sel-con@00c4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - /* reg[7:0]: reserved */ - - aclk_vcodec_pre_div: aclk_vcodec_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_vcodec_pre>; - clock-output-names = "aclk_vcodec_pre"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[13]: reserved */ - - aclk_vcodec_pre: aclk_vcodec_pre_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>; - clock-output-names = "aclk_vcodec_pre"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con34: sel-con@00cc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00cc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_gpu_div: clk_gpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_gpu>; - clock-output-names = "clk_gpu"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[7:5]: reserved */ - - clk_gpu: clk_gpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&dummy>, <&dummy>, <&clk_gpll>; - clock-output-names = "clk_gpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15:10]: reserved */ - - }; - - }; - - - /* Gate control regs */ - clk_gate_cons { - compatible = "rockchip,rk-gate-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges ; - - clk_gates0: gate-clk@00d0{ - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d0 0x4>; - clocks = - <&clk_core>, <&clk_gpll>, - <&clk_dpll>, <&aclk_cpu_pre>, - - <&aclk_cpu_pre>, <&aclk_cpu_pre>, - <&clk_gpll>, <&clk_core>, - - <&clk_gpll>, <&clk_i2s_pll>, - <&i2s_frac>, <&hclk_vio_pre>, - - <&dummy>, <&clk_i2s_out>, - <&clk_i2s>, <&dummy>; - - clock-output-names = - "pclk_dbg", "reserved", /* do not use bit1 = "cpu_gpll" */ - "reserved", "aclk_cpu_pre", - - "hclk_cpu_pre", "pclk_cpu_pre", - "reserved", "aclk_core_pre", - - "reserved", "clk_i2s_pll", - "i2s_frac", "hclk_vio_pre", - - "clk_cryto", "clk_i2s_out", - "clk_i2s", "clk_testout"; - rockchip,suspend-clkgating-setting=<0x19ff 0x19ff>; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@00d4{ - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d4 0x4>; - clocks = - <&clk_timer0>, <&clk_timer1>, - <&dummy>, <&jtag_tck>, - - <&aclk_vio_pre>, <&xin12m>, - <&dummy>, <&dummy>, - - <&clk_uart0_div>, <&uart0_frac>, - <&clk_uart1_div>, <&uart1_frac>, - - <&clk_uart2_div>, <&uart2_frac>, - <&dummy>, <&dummy>; - - clock-output-names = - "clk_timer0", "clk_timer1", - "reserved", "clk_jatg", - - "aclk_vio_pre", "clk_otgphy0", - "clk_otgphy1", "reserved", - - "clk_uart0_div", "uart0_frac", - "clk_uart1_div", "uart1_frac", - - "clk_uart2_div", "uart2_frac", - "reserved", "reserved"; - - rockchip,suspend-clkgating-setting=<0xc0af 0xc0af>; - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@00d8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d8 0x4>; - clocks = - <&aclk_peri_pre>, <&aclk_peri_pre>, - <&aclk_peri_pre>, <&aclk_peri_pre>, - - <&clk_timer2>, <&clk_timer3>, - <&clk_mac_ref>, <&dummy>, - - <&dummy>, <&clk_spi0>, - <&clk_spdif_pll>, <&clk_sdmmc0>, - - <&spdif_frac>, <&clk_sdio>, - <&clk_emmc>, <&dummy>; - - clock-output-names = - "aclk_peri", "aclk_peri_pre", - "hclk_peri_pre", "pclk_peri_pre", - - "clk_timer2", "clk_timer3", - "clk_mac", "reserved", - - "reserved", "clk_spi0", - "clk_spdif_pll", "clk_sdmmc0", - - "spdif_frac", "clk_sdio", - "clk_emmc", "reserved"; - rockchip,suspend-clkgating-setting=<0x81bf 0x81bf>; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@00dc { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00dc 0x4>; - clocks = - <&dummy>, <&dummy>, - <&dclk_lcdc1>, <&dummy>, - - <&dummy>, <&hclk_peri_pre>, - <&dummy>, <&dummy>, - - <&pclk_cpu_pre>, <&dummy>, - <&dummy>, <&aclk_vcodec_pre>, - - <&aclk_vcodec_pre>, <&clk_gpu>, - <&hclk_peri_pre>, <&dummy>; - - clock-output-names = - "reserved", "reserved", - "dclk_lcdc1", "reserved", - - "reserved", "g_hclk_mac", - "reserved", "reserved", - - "g_pclk_hdmi", "reserved", - "reserved", "aclk_vcodec_pre", - - "hclk_vcodec", "clk_gpu", - "g_hclk_sfc", "reserved"; - rockchip,suspend-clkgating-setting=<0xa7fb 0xa7fb>; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@00e0{ - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e0 0x4>; - clocks = - <&hclk_peri_pre>, <&pclk_peri_pre>, - <&aclk_peri_pre>, <&aclk_peri_pre>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&aclk_cpu_pre>, <&dummy>, - - <&aclk_cpu_pre>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_hp_axi_matrix", "g_pp_axi_matrix", - "g_aclk_cpu_peri", "g_ap_axi_matrix", - - "reserved", "g_hclk_mac", - "reserved", "reserved", - - "reserved", "reserved", - "g_aclk_strc_sys", "reserved", - - /* Not use these ddr gates */ - "g_aclk_intmem", "reserved", - "reserved", "reserved"; - - rockchip,suspend-clkgating-setting = <0xffff 0xffff>; - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@00e4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e4 0x4>; - clocks = - <&dummy>, <&aclk_peri_pre>, - <&pclk_peri_pre>, <&dummy>, - - <&pclk_cpu_pre>, <&dummy>, - <&hclk_cpu_pre>, <&pclk_cpu_pre>, - - <&dummy>, <&hclk_peri_pre>, - <&hclk_peri_pre>, <&hclk_peri_pre>, - - <&dummy>, <&hclk_peri_pre>, - <&pclk_cpu_pre>, <&dummy>; - - clock-output-names = - "reserved", "g_aclk_dmac2", - "g_pclk_efuse", "reserved", - - "g_pclk_grf", "reserved", - "g_hclk_rom", "g_pclk_ddrupctl", - - "reserved", "g_hclk_nandc", - "g_hclk_sdmmc0", "g_hclk_sdio", - - "reserved", "g_hclk_otg0", - "g_pclk_acodec", "reserved"; - - rockchip,suspend-clkgating-setting = <0x91fd 0x91fd>; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@00e8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e8 0x4>; - clocks = - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&hclk_vio_pre>, <&aclk_vio_pre>, - <&dummy>, <&dummy>; - - clock-output-names = - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "g_hclk_vio_bus", "g_aclk_vio", - "reserved", "reserved"; - - rockchip,suspend-clkgating-setting = <0xffff 0xffff>; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@00ec { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00ec 0x4>; - clocks = - <&hclk_peri_pre>, <&dummy>, - <&hclk_peri_pre>, <&hclk_peri_pre>, - - <&dummy>, <&dummy>, - <&dummy>, <&pclk_peri_pre>, - - <&dummy>, <&dummy>, - <&pclk_peri_pre>, <&dummy>, - - <&pclk_peri_pre>, <&dummy>, - <&dummy>, <&pclk_peri_pre>; - - clock-output-names = - "g_hclk_emmc", "reserved", - "g_hclk_i2s", "g_hclk_otg1", - - "reserved", "reserved", - "reserved", "g_pclk_timer0", - - "reserved", "reserved", - "g_pclk_pwm", "reserved", - - "g_pclk_spi", "reserved", - "reserved", "g_pclk_wdt"; - - rockchip,suspend-clkgating-setting = <0x6ff2 0x6ff2>; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@00f0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f0 0x4>; - clocks = - <&pclk_peri_pre>, <&pclk_peri_pre>, - <&pclk_peri_pre>, <&dummy>, - - <&pclk_peri_pre>, <&pclk_peri_pre>, - <&pclk_peri_pre>, <&dummy>, - - <&dummy>, <&pclk_peri_pre>, - <&pclk_peri_pre>, <&pclk_peri_pre>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_pclk_uart0", "g_pclk_uart1", - "g_pclk_uart2", "reserved", - - "g_pclk_i2c0", "g_pclk_i2c1", - "g_pclk_i2c2", "reserved", - - "reserved", "g_pclk_gpio0", - "g_pclk_gpio1", "g_pclk_gpio2", - - "reserved", "reserved", - "reserved", "reserved"; - - rockchip,suspend-clkgating-setting=<0xf38c 0xf38c>; - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@00f4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f4 0x4>; - clocks = - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&hclk_vio_pre>, - <&aclk_vio_pre>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&hclk_peri_pre>, - <&hclk_peri_pre>, <&aclk_peri_pre>; - - clock-output-names = - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "g_hclk_lcdc", - "g_aclk_lcdc", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "g_hclk_usb_peri", - "g_hclk_pe_arbi", "g_aclk_peri_niu"; - - rockchip,suspend-clkgating-setting=<0xdf9f 0xdf9f>; - - #clock-cells = <1>; - }; - - clk_gates10: gate-clk@00f8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f8 0x4>; - clocks = - <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - - <&clk_nandc>, <&clk_sfc>, - <&clk_hevc_core>, <&dummy>, - - <&clk_dpll>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_clk_pvtm_core", "g_clk_pvtm_gpu", - "g_pvtm_video", "reserved", - - "clk_nandc", "clk_sfc", - "clk_hevc_core", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - - rockchip,suspend-clkgating-setting = <0x0077 0x0077>; /* pwm logic vol */ - - #clock-cells = <1>; - }; - - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi deleted file mode 100755 index 2c7f731149dc..000000000000 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ /dev/null @@ -1,1488 +0,0 @@ -/* - * Copyright (C) 2013 ROCKCHIP, Inc. - * Author: chenxing - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include - -/{ - clocks { - compatible = "rockchip,rk-clocks"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000000 0x0100>; - - fixed_rate_cons { - compatible = "rockchip,rk-fixed-rate-cons"; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "xin24m"; - clock-frequency = <24000000>; - }; - - xin12m: xin12m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clocks = <&xin24m>; - clock-output-names = "xin12m"; - clock-frequency = <12000000>; - }; - - dummy: dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "dummy"; - clock-frequency = <0>; - }; - - - rmii_clkin: rmii_clkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "rmii_clkin"; - clock-frequency = <0>; - }; - - clk_hsadc_ext: clk_hsadc_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "clk_hsadc_ext"; - clock-frequency = <0>; - }; - - clk_cif_in: clk_cif_in { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "clk_cif_in"; - clock-frequency = <0>; - }; - - }; - - fixed_factor_cons { - compatible = "rockchip,rk-fixed-factor-cons"; - - otgphy0_480m: otgphy0_480m { - compatible = "fixed-factor-clock"; - clocks = <&clk_gates1 5>; - clock-output-names = "otgphy0_480m"; - clock-div = <1>; - clock-mult = <20>; - #clock-cells = <0>; - }; - - otgphy1_480m: otgphy1_480m { - compatible = "fixed-factor-clock"; - clocks = <&clk_gates1 6>; - clock-output-names = "otgphy1_480m"; - clock-div = <1>; - clock-mult = <20>; - #clock-cells = <0>; - }; - - }; - - clock_regs { - compatible = "rockchip,rk-clock-regs"; - reg = <0x0000 0x3ff>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* PLL control regs */ - pll_cons { - compatible = "rockchip,rk-pll-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges ; - - clk_apll: pll-clk@0000 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0000 0x10>; - mode-reg = <0x0040 0>; - status-reg = <0x00ac 6>; - clocks = <&xin24m>; - clock-output-names = "clk_apll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - clk_dpll: pll-clk@0010 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0010 0x10>; - mode-reg = <0x0040 4>; - status-reg = <0x00ac 5>; - clocks = <&xin24m>; - clock-output-names = "clk_dpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - clk_cpll: pll-clk@0020 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0020 0x10>; - mode-reg = <0x0040 8>; - status-reg = <0x00ac 7>; - clocks = <&xin24m>; - clock-output-names = "clk_cpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_gpll: pll-clk@0030 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0030 0x10>; - mode-reg = <0x0040 12>; - status-reg = <0x00ac 8>; - clocks = <&xin24m>; - clock-output-names = "clk_gpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - /* Select control regs */ - clk_sel_cons { - compatible = "rockchip,rk-sel-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_sel_con0: sel-con@0044 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0044 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_cpu_div: aclk_cpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_cpu>; - clock-output-names = "aclk_cpu"; - #clock-cells = <0>; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - aclk_cpu: aclk_cpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 1>; - clocks = <&clk_apll>, <&clk_gpll>; - clock-output-names = "aclk_cpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_core_peri: clk_core_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <6 2>; - clocks = <&clk_core>; - clock-output-names = "clk_core_peri"; - rockchip,div-type = ; - rockchip,clkops-idx = ; - #clock-cells = <0>; - rockchip,div-relations = <0x0 2 - 0x1 4 - 0x2 8 - 0x3 16>; - }; - - clk_core: clk_core_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 1>; - clocks = <&clk_apll>, - <&clk_gates0 1>; - clock-output-names = "clk_core"; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_core_div: clk_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <9 5>; - clocks = <&clk_core>; - clock-output-names = "clk_core"; - rockchip,div-type = ; - rockchip,clkops-idx = ; - #clock-cells = <0>; - }; - - /* reg[15:14]: reserved */ - - }; - - clk_sel_con1: sel-con@0048 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0048 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - /* reg[2:0]: reserved */ - - aclk_core: aclk_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <3 3>; - clocks = <&clk_core>; - clock-output-names = "aclk_core"; - #clock-cells = <0>; - rockchip,div-type = ; - rockchip,clkops-idx = ; - rockchip,div-relations = <0x0 1 - 0x1 2 - 0x2 3 - 0x3 4 - 0x4 8>; - }; - - /* reg[7:6]: reserved */ - - hclk_cpu: hclk_cpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_cpu>; - rockchip,div-type = ; - clock-output-names = "hclk_cpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[11:10]: reserved */ - - pclk_cpu: pclk_cpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 2>; - clocks = <&aclk_cpu>; - rockchip,div-type = ; - clock-output-names = "pclk_cpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - pclk_ahb2apb: pclk_ahb2apb_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <14 2>; - clocks = <&hclk_cpu>; - rockchip,div-type = ; - clock-output-names = "pclk_ahb2apb"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - clk_sel_con2: sel-con@004c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x004c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - /* reg[14:0]: reserved */ - - clk_i2s_pll_mux: clk_i2s_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_gpll>, <&clk_cpll>; - clock-output-names = "clk_i2s_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con3: sel-con@0050 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0050 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_i2s_div: clk_i2s_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_i2s_pll_mux>; - rockchip,div-type = ; - clock-output-names = "clk_i2s_div"; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_i2s: clk_i2s_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_i2s_div>, <&clk_i2s_frac>, <&xin12m>; - clock-output-names = "clk_i2s"; - rockchip,clkops-idx = ; - rockchip,flags = ; - #clock-cells = <0>; - }; - - /* reg[15:10]: reserved */ - }; - - /* clk_sel_con4: reserved */ - - clk_sel_con5: sel-con@0058 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0058 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_spdif_div: clk_spdif_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_i2s_pll_mux>; - rockchip,div-type = ; - clock-output-names = "clk_spdif_div"; - /* spdif same as i2s */ - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_spdif: clk_spdif_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_spdif_div>, <&clk_spdif_frac>, <&xin12m>; - clock-output-names = "clk_spdif"; - rockchip,clkops-idx = ; - rockchip,flags = ; - #clock-cells = <0>; - }; - - /* reg[15:10]: reserved */ - }; - - /* clk_sel_con6: reserved */ - - clk_sel_con7: sel-con@0060 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0060 0x4>; - #address-cells = <1>; - #size-cells = <1>; - clk_i2s_frac: clk_i2s_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_i2s_div>; - clock-output-names = "clk_i2s_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - }; - - /* clk_sel_con8: reserved */ - - clk_sel_con9: sel-con@0068 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0068 0x4>; - #address-cells = <1>; - #size-cells = <1>; - clk_spdif_frac: clk_spdif_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_spdif_div>; - clock-output-names = "clk_spdif_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - }; - - clk_sel_con10: sel-con@006c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x006c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_peri_div: aclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_peri>; - clock-output-names = "aclk_peri"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[7:5]: reserved */ - - hclk_peri: hclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_peri>; - clock-output-names = "hclk_peri"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[11:10]: reserved */ - - pclk_peri: pclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 2>; - clocks = <&aclk_peri>; - clock-output-names = "pclk_peri"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[14]: reserved */ - - aclk_peri: aclk_peri_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "aclk_peri"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con11: sel-con@0070 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sdmmc: clk_sdmmc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&hclk_peri>; - clock-output-names = "clk_sdmmc"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[7:6]: reserved */ - - clk_ehci1phy12m: ehci1_phy_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 6>; - clocks = <&clk_ehci1phy480m>; - clock-output-names = "clk_ehci1phy12m"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[15:14]: reserved */ - - }; - - clk_sel_con12: sel-con@0074 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sdio: clk_sdio_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&hclk_peri>; - clock-output-names = "clk_sdio"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[7:6]: reserved */ - - clk_emmc: clk_emmc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 6>; - clocks = <&hclk_peri>; - clock-output-names = "clk_emmc"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[14]: reserved */ - - clk_uart_pll_mux: clk_uart_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_gpll>, <&clk_cpll>; - clock-output-names = "clk_uart_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con13: sel-con@0078 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart0_div: clk_uart0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart_pll_mux>; - clock-output-names = "clk_uart0_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart0: clk_uart0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart0_div>, <&clk_uart0_frac>, - <&xin24m>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - clock-output-names = "clk_uart0"; - #clock-cells = <0>; - }; - - /* reg[15:10]: reserved */ - - }; - - clk_sel_con14: sel-con@007c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x007c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart1_div: clk_uart1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart_pll_mux>; - clock-output-names = "clk_uart1_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart1: clk_uart1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart1_div>, <&clk_uart1_frac>, - <&xin24m>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - clock-output-names = "clk_uart1"; - #clock-cells = <0>; - }; - - /* reg[15:10]: reserved */ - - }; - - clk_sel_con15: sel-con@0080 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0080 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart2_div: clk_uart2_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart_pll_mux>; - clock-output-names = "clk_uart2_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart2: clk_uart2_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart2_div>, <&clk_uart2_frac>, - <&xin24m>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - clock-output-names = "clk_uart2"; - #clock-cells = <0>; - }; - - /* reg[15:10]: reserved */ - - }; - - clk_sel_con16: sel-con@0084 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0084 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart3_div: clk_uart3_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart_pll_mux>; - clock-output-names = "clk_uart3_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart3: clk_uart3_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart3_div>, <&clk_uart3_frac>, - <&xin24m>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - clock-output-names = "clk_uart3"; - #clock-cells = <0>; - }; - - /* reg[15:10]: reserved */ - - }; - - clk_sel_con17: sel-con@0088 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0088 0x4>; - #address-cells = <1>; - #size-cells = <1>; - clk_uart0_frac: clk_uart0_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart0_div>; - clock-output-names = "clk_uart0_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - clk_sel_con18: sel-con@008c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x008c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - clk_uart1_frac: clk_uart1_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart1_div>; - clock-output-names = "clk_uart1_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - clk_sel_con19: sel-con@0090 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0090 0x4>; - #address-cells = <1>; - #size-cells = <1>; - clk_uart2_frac: clk_uart2_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart2_div>; - clock-output-names = "clk_uart2_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - clk_sel_con20: sel-con@0094 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0094 0x4>; - #address-cells = <1>; - #size-cells = <1>; - clk_uart3_frac: clk_uart3_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart3_div>; - clock-output-names = "clk_uart3_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con21: sel-con@0098 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0098 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_mac_pll_mux: clk_mac_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&clk_gpll>, <&clk_dpll>; - clock-output-names = "clk_mac_pll"; - #clock-cells = <0>; - }; - - /* reg[3:1]: reserved */ - - clk_mac: clk_mac_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <4 1>; - clocks = <&clk_mac_pll_mux>, <&rmii_clkin>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - clock-output-names = "clk_mac"; - #clock-cells = <0>; - }; - - /* reg[7:5]: reserved */ - - clk_mac_pll_div: clk_mac_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_mac_pll_mux>; - clock-output-names = "clk_mac_pll"; - rockchip,clkops-idx = - ; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[15:13]: reserved */ - }; - - clk_sel_con22: sel-con@009c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x009c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_hsadc_pll_mux: clk_hsadc_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&clk_gpll>, <&clk_cpll>; - clock-output-names = "clk_hsadc_pll"; - #clock-cells = <0>; - }; - - /* reg[3:1]: reserved */ - - clk_hsadc: clk_hsadc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <4 2>; - clocks = <&clk_hsadc_pll_mux>, <&clk_hsadc_frac>, - <&clk_hsadc_ext>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - clock-output-names = "clk_hsadc"; - #clock-cells = <0>; - }; - - /* reg[6]: reserved */ - - clk_hsadc_inv: clk_hsadc_inv { - compatible = "rockchip,rk3188-inv-con"; - rockchip,bits = <7 1>; - clocks = <&clk_hsadc>; - }; - - clk_hsadc_div: clk_hsadc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&clk_hsadc_pll_mux>; - clock-output-names = "clk_hsadc_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - }; - - clk_sel_con23: sel-con@00a0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_hsadc_frac: clk_hsadc_frac{ - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_hsadc_pll_mux>; - clock-output-names = "clk_hsadc_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con24: sel-con@00a4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - clk_saradc: clk_saradc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&xin24m>; - clock-output-names = "clk_saradc"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - }; - - clk_sel_con25: sel-con@00a8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_spi0: clk_spi0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&pclk_peri>; - clock-output-names = "clk_spi0"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - /* reg[7]: reserved */ - clk_spi1: clk_spi1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 7>; - clocks = <&pclk_peri>; - clock-output-names = "clk_spi1"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - /* reg[15]: reserved */ - }; - - clk_sel_con26: sel-con@00ac { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00ac 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_ddr_div: clk_ddr_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 2>; - clocks = <&clk_ddr>; - clock-output-names = "clk_ddr"; - rockchip,div-type = ; - rockchip,clkops-idx = ; - #clock-cells = <0>; - }; - - /* reg[7:2]: reserved */ - - clk_ddr: clk_ddr_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 1>; - clocks = <&clk_dpll>, - <&clk_gates1 7>; - clock-output-names = "clk_ddr"; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - #clock-cells = <0>; - }; - - /* reg[15:9]: reserved */ - }; - - clk_sel_con27: sel-con@00b0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - dclk_lcdc0: dclk_lcdc0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "dclk_lcdc0"; - #clock-cells = <0>; - }; - - /* reg[7:1]: reserved */ - - dclk_lcdc0_div: dclk_lcdc0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&dclk_lcdc0>; - clock-output-names = "dclk_lcdc0"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - - clk_sel_con28: sel-con@00b4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - dclk_lcdc1: dclk_lcdc1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "dclk_lcdc1"; - #clock-cells = <0>; - }; - - /* reg[7:1]: reserved */ - - dclk_lcdc1_div: dclk_lcdc1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&dclk_lcdc1>; - clock-output-names = "dclk_lcdc1"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con29: sel-con@00b8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - cif_out_pll_mux: cif_out_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "cif_out_pll"; - #clock-cells = <0>; - }; - - cif0_out_div: cif0_out_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <1 5>; - clocks = <&cif_out_pll_mux>; - clock-output-names = "cif_out_pll"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[6]: reserved */ - - clk_cif0: cif0_out_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&cif_out_pll_mux>, <&xin24m>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - clock-output-names = "clk_cif0"; - #clock-cells = <0>; - }; - - /* reg[15:8]: reserved */ - }; - - clk_sel_con30: sel-con@00bc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00bc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_ehci1phy480m: clk_ehci1phy480m_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&otgphy0_480m>, <&otgphy1_480m>, - <&clk_gpll>, <&clk_cpll>; - clock-output-names = "clk_ehci1phy480m"; - #clock-cells = <0>; - }; - - /* reg[7:2]: reserved */ - - /* inv here?????? */ - - /* reg[15:9]: reserved */ - }; - - clk_sel_con31: sel-con@00c0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_lcdc0_pre_div: aclk_lcdc0_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_lcdc0>; - clock-output-names = "aclk_lcdc0"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[6:5]: reserved */ - - aclk_lcdc0: aclk_lcdc0_pre_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "aclk_lcdc0"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_lcdc1_pre_div: aclk_lcdc1_pre_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_lcdc1>; - clock-output-names = "aclk_lcdc1"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[14:13]: reserved */ - - aclk_lcdc1: aclk_lcdc1_pre_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "aclk_lcdc1"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con32: sel-con@00c4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_vepu_div: aclk_vepu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_vepu>; - clock-output-names = "clk_vepu"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[6:5]: reserved */ - - clk_vepu: aclk_vepu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_vepu"; - #clock-cells = <0>; - }; - - aclk_vdpu_div: aclk_vdpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_vdpu>; - clock-output-names = "clk_vdpu"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[14:13]: reserved */ - - clk_vdpu: aclk_vdpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_vdpu"; - #clock-cells = <0>; - }; - }; - - clk_sel_con34: sel-con@00cc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00cc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_gpu_div: aclk_gpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_gpu>; - clock-output-names = "clk_gpu"; - rockchip,div-type = ; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - /* reg[6:5]: reserved */ - - clk_gpu: aclk_gpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_gpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15:8]: reserved */ - }; - }; - - /* Gate control regs */ - clk_gate_cons { - compatible = "rockchip,rk-gate-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges ; - - clk_gates0: gate-clk@00d0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d0 0x4>; - clocks = <&clk_core_peri>, <&clk_gpll>, - <&clk_dpll>, <&aclk_cpu>, - - <&hclk_cpu>, <&pclk_cpu>, - <&pclk_cpu>, <&aclk_core>, - - <&dummy>, <&clk_i2s_div>, - <&clk_i2s_frac>, <&dummy>, - - <&dummy>, <&clk_spdif_div>, - <&clk_spdif_frac>, <&dummy>; - - clock-output-names = - "clk_core_peri", "clk_arm_gpll", - "clk_dpll", "aclk_cpu", - - "hclk_cpu", "pclk_cpu", - "g_atclk_cpu", "aclk_core", - - "reserved", "clk_i2s_div", - "clk_i2s_frac", "reserved", - - "reserved", "clk_spdif_div", - "clk_spdif_frac", "g_testclk"; - rockchip,suspend-clkgating-setting=<0x00bf 0x00bf>; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@00d4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - - <&aclk_lcdc1>, <&xin24m>, - <&xin24m>, <&clk_gpll>, - - <&clk_uart0_div>, <&clk_uart0_frac>, - <&clk_uart1_div>, <&clk_uart1_frac>, - - <&clk_uart2_div>, <&clk_uart2_frac>, - <&clk_uart3_div>, <&clk_uart3_frac>; - - clock-output-names = - "timer0", "timer1", - "timer3", "g_jtag", - - "aclk_lcdc1", "g_otgphy0", - "g_otgphy1", "clk_ddr_gpll", - - "clk_uart0_div", "clk_uart0_frac", - "clk_uart1_div", "clk_uart1_frac", - - "clk_uart2_div", "clk_uart2_frac", - "clk_uart3_div", "clk_uart3_frac"; - rockchip,suspend-clkgating-setting=<0x0 0x0>; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@00d8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d8 0x4>; - clocks = <&aclk_peri>, <&aclk_peri>, - <&hclk_peri>, <&pclk_peri>, - - <&hclk_peri>, <&clk_mac_pll_mux>, - <&clk_hsadc_pll_mux>, <&clk_hsadc_frac>, - - <&clk_saradc>, <&clk_spi0>, - <&clk_spi1>, <&clk_sdmmc>, - - <&dummy>, <&clk_sdio>, - <&clk_emmc>, <&dummy>; - - clock-output-names = - "aclk_peri", "g_aclk_peri", - "hclk_peri", "pclk_peri", - - "g_smc_src", "clk_mac_pll", - "clk_hsadc_pll", "clk_hsadc_frac", - - "clk_saradc", "clk_spi0", - "clk_spi1", "clk_sdmmc", - - "g_mac_lbtest", "clk_sdio", - "clk_emmc", "reserved"; - //rockchip,suspend-clkgating-setting=<0x1f 0x1b>; - rockchip,suspend-clkgating-setting=<0x1f 0x1b>; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@00dc { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00dc 0x4>; - clocks = <&aclk_lcdc0>, <&dclk_lcdc0>, - <&dclk_lcdc1>, <&clk_cif_in>, - - <&xin24m>, <&xin24m>, - <&clk_ehci1phy480m>, <&clk_cif0>, - - <&xin24m>, <&clk_vepu>, - <&clk_vepu>, <&clk_vdpu>, - - <&clk_vdpu>, <&dummy>, - <&xin24m>, <&clk_gpu>; - - clock-output-names = - "aclk_lcdc0", "dclk_lcdc0", - "dclk_lcdc1", "g_clk_cif_in", - - /* - * FIXME: cif_out_pll can be set to - * clk_cif as virtual - */ - "timer2", "timer4", - "clk_ehci1phy480m", "clk_cif0", - - "timer5", "clk_vepu", - "g_h_vepu", "clk_vdpu", - - "g_h_vdpu", "reserved", - "timer6", "clk_gpu"; - rockchip,suspend-clkgating-setting=<0x0 0x0>; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@00e0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e0 0x4>; - clocks = <&hclk_peri>, <&pclk_peri>, - <&aclk_peri>, <&aclk_peri>, - - <&aclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&hclk_peri>, - - <&hclk_cpu>, <&hclk_cpu>, - <&aclk_cpu>, <&dummy>, - - <&aclk_cpu>, <&dummy>, - <&hclk_cpu>, <&hclk_cpu>; - - /* - * g_ap: gate_aclk_peri_... - * g_hp: gate_hclk_peri_... - * g_pp: gate_pclk_peri_... - */ - clock-output-names = - "g_hp_axi_matrix", "g_pp_axi_matrix", - "g_a_cpu_peri", "g_ap_axi_matrix", - - "g_a_peri_niu", "g_h_usb_peri", - "g_hp_ahb_arbi", "g_h_emem_peri", - - "g_h_cpubus", "g_h_ahb2apb", - "g_a_strc_sys", "reserved", - - "g_a_intmem", "reserved", - "g_h_imem1", "g_h_imem0"; - - //rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>; - rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>; - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@00e4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e4 0x4>; - clocks = <&aclk_cpu>, <&aclk_peri>, - <&pclk_cpu>, <&pclk_cpu>, - - <&pclk_cpu>, <&pclk_cpu>, - <&hclk_cpu>, <&pclk_cpu>, - - <&aclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&hclk_peri>, - - <&hclk_peri>, <&hclk_peri>; - - clock-output-names = - "g_a_dmac1", "g_a_dmac2", - "g_p_efuse", "g_p_tzpc", - - "g_p_grf", "g_p_pmu", - "g_h_rom", "g_p_ddrupctl", - - "g_a_smc", "g_h_nandc", - "g_h_sdmmc0", "g_h_sdio", - - "g_h_emmc", "g_h_otg0"; - rockchip,suspend-clkgating-setting=<0x80 0x80>; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@00e8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e8 0x4>; - clocks = <&clk_gates6 13>, <&hclk_cpu>, - <&hclk_cpu>, <&clk_gates9 5>, - - <&hclk_cpu>, <&clk_gates6 13>, - <&dummy>, <&dummy>, - - <&clk_gates6 13>, <&hclk_cpu>, - <&hclk_cpu>, <&clk_gates9 5>, - - <&hclk_cpu>, <&aclk_lcdc0>; - - clock-output-names = - "g_a_lcdc0", "g_h_lcdc0", - "g_h_lcdc1", "g_a_lcdc1", - - "g_h_cif0", "g_a_cif0", - "reserved", "reserved", - - "g_a_ipp", "g_h_ipp", - "g_h_rga", "g_a_rga", - - "g_h_vio_bus", "g_a_vio0"; - - rockchip,suspend-clkgating-setting=<0x0 0x0>; - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@00ec { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00ec 0x4>; - clocks = <&hclk_peri>, <&hclk_cpu>, - <&hclk_cpu>, <&hclk_peri>, - - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&pclk_cpu>, - - <&dummy>, <&pclk_cpu>, - <&pclk_cpu>, <&pclk_peri>, - - <&pclk_peri>, <&pclk_peri>, - <&pclk_peri>, <&pclk_peri>; - - clock-output-names = - "g_h_emac", "g_h_spdif", - "g_h_i2s0_2ch", "g_h_otg1", - - "g_h_ehci1", "g_h_hsadc", - "g_h_pidf", "g_p_timer0", - - "reserved", "g_p_timer2", - "g_p_pwm01", "g_p_pwm23", - - "g_p_spi0", "g_p_spi1", - "g_p_saradc", "g_p_wdt"; - rockchip,suspend-clkgating-setting=<0x0 0x0>; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@00f0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f0 0x4>; - clocks = <&pclk_ahb2apb>, <&pclk_ahb2apb>, - <&pclk_peri>, <&pclk_peri>, - - <&pclk_cpu>, <&pclk_cpu>, - <&pclk_peri>, <&pclk_peri>, - - <&pclk_peri>, <&pclk_cpu>, - <&pclk_cpu>, <&pclk_cpu>, - - <&pclk_peri>, <&aclk_peri>; - - clock-output-names = - "g_p_uart0", "g_p_uart1", - "g_p_uart2", "g_p_uart3", - - "g_p_i2c0", "g_p_i2c1", - "g_p_i2c2", "g_p_i2c3", - - "g_p_i2c4", "g_p_gpio0", - "g_p_gpio1", "g_p_gpio2", - - "g_p_gpio3", "g_a_gps"; - rockchip,suspend-clkgating-setting=<0x200 0x200>; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@00f4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f4 0x4>; - clocks = <&clk_core>, <&pclk_cpu>, - <&clk_gates0 6>, <&clk_gates0 6>, - - <&clk_core>, <&aclk_lcdc1>, - <&pclk_cpu>, <&clk_gpu>; - - clock-output-names = - "g_clk_core_dbg", "g_p_dbg", - "g_clk_trace", "g_atclk", - - "g_clk_l2c", "g_a_vio1", - "g_p_ddrpubl", "g_a_gpu"; - rockchip,suspend-clkgating-setting=<0x50 0x50>; - - #clock-cells = <1>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi deleted file mode 100755 index ce6d3395e83c..000000000000 --- a/arch/arm/boot/dts/rk3288-clocks.dtsi +++ /dev/null @@ -1,2781 +0,0 @@ -/* - * Copyright (C) 2014 ROCKCHIP, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include - -/{ - clocks { - compatible = "rockchip,rk-clocks"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xFF760000 0x01b0>; - - fixed_rate_cons { - compatible = "rockchip,rk-fixed-rate-cons"; - - xin24m: xin24m { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "xin24m"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - xin12m: xin12m { - compatible = "rockchip,rk-fixed-clock"; - clocks = <&xin24m>; - clock-output-names = "xin12m"; - clock-frequency = <12000000>; - #clock-cells = <0>; - }; - - xin32k: xin32k { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "xin32k"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - io_27m_in: io_27m_in { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "io_27m_in"; - clock-frequency = <27000000>; - #clock-cells = <0>; - }; - - dummy: dummy { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "dummy"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy_cpll: dummy_cpll { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "dummy_cpll"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - i2s_clkin: i2s_clkin { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "i2s_clkin"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - edp_24m_clkin: edp_24m_clkin { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "edp_24m_clkin"; - clock-frequency = <0>; - }; - - gmac_clkin: gmac_clkin { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "gmac_clkin"; - clock-frequency = <125000000>; - }; - - clk_hsadc_ext: clk_hsadc_ext { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "clk_hsadc_ext"; - clock-frequency = <0>; - }; - - jtag_clkin: jtag_clkin { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "jtag_clkin"; - clock-frequency = <0>; - }; - - pclkin_cif: pclkin_cif { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "pclkin_cif"; - clock-frequency = <0>; - }; - - pclkin_isp: pclkin_isp { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "pclkin_isp"; - clock-frequency = <0>; - }; - - hsadc_0_tsp: hsadc_0_tsp { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "hsadc_0_tsp"; - clock-frequency = <0>; - }; - - hsadc_1_tsp: hsadc_1_tsp { - compatible = "rockchip,rk-fixed-clock"; - #clock-cells = <0>; - clock-output-names = "hsadc_1_tsp"; - clock-frequency = <0>; - }; - - }; - - fixed_factor_cons { - compatible = "rockchip,rk-fixed-factor-cons"; - - otgphy0_480m: otgphy0_480m { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_gates13 4>; - clock-output-names = "otgphy0_480m"; - clock-div = <1>; - clock-mult = <20>; - #clock-cells = <0>; - }; - - otgphy1_480m: otgphy1_480m { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_gates13 5>; - clock-output-names = "otgphy1_480m"; - clock-div = <1>; - clock-mult = <20>; - #clock-cells = <0>; - }; - - otgphy2_480m: otgphy2_480m { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_gates13 6>; - clock-output-names = "otgphy2_480m"; - clock-div = <1>; - clock-mult = <20>; - #clock-cells = <0>; - }; - - clk_hsadc_inv: clk_hsadc_inv { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_hsadc_out>; - clock-output-names = "clk_hsadc_inv"; - clock-div = <1>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - pclkin_cif_inv: pclkin_cif_inv { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_gates16 0>; - clock-output-names = "pclkin_cif_inv"; - clock-div = <1>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - pclkin_isp_inv: pclkin_isp_inv { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_gates16 3>; - clock-output-names = "pclkin_isp_inv"; - clock-div = <1>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - hclk_vepu: hclk_vepu { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_vepu>; - clock-output-names = "hclk_vepu"; - clock-div = <4>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - hclk_vdpu: hclk_vdpu { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&clk_vdpu>; - clock-output-names = "hclk_vdpu"; - clock-div = <4>; - clock-mult = <1>; - #clock-cells = <0>; - }; - }; - - pd_cons { - compatible = "rockchip,rk-pd-cons"; - - pd_gpu: pd_gpu { - compatible = "rockchip,rk-pd-clock"; - clock-output-names = "pd_gpu"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_video: pd_video { - compatible = "rockchip,rk-pd-clock"; - clock-output-names = "pd_video"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_vio: pd_vio { - compatible = "rockchip,rk-pd-clock"; - clock-output-names = "pd_vio"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_hevc: pd_hevc { - compatible = "rockchip,rk-pd-clock"; - clock-output-names = "pd_hevc"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_edp: pd_edp { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_edp"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_vop0: pd_vop0 { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_vop0"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_vop1: pd_vop1 { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_vop1"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_isp: pd_isp { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_isp"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_iep: pd_iep { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_iep"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_rga: pd_rga { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_rga"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_mipicsi: pd_mipicsi { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_mipicsi"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_mipidsi: pd_mipidsi { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_mipidsi"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_lvds: pd_lvds { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_lvds"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - pd_hdmi: pd_hdmi { - compatible = "rockchip,rk-pd-clock"; - clocks = <&pd_vio>; - clock-output-names = "pd_hdmi"; - rockchip,pd-id = ; - #clock-cells = <0>; - }; - - }; - - - clock_regs { - compatible = "rockchip,rk-clock-regs"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0000 0x3ff>; - ranges; - - /* PLL control regs */ - pll_cons { - compatible = "rockchip,rk-pll-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges ; - - clk_apll: pll-clk@0000 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0000 0x10>; - mode-reg = <0x0050 0>; - status-reg = <0x0284 6>; - clocks = <&xin24m>; - clock-output-names = "clk_apll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - clk_dpll: pll-clk@0010 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0010 0x10>; - mode-reg = <0x0050 4>; - status-reg = <0x0284 5>; - clocks = <&xin24m>; - clock-output-names = "clk_dpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - clk_cpll: pll-clk@0020 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0020 0x10>; - mode-reg = <0x0050 8>; - status-reg = <0x0284 7>; - clocks = <&xin24m>; - clock-output-names = "clk_cpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_gpll: pll-clk@0030 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0030 0x10>; - mode-reg = <0x0050 12>; - status-reg = <0x0284 8>; - clocks = <&xin24m>; - clock-output-names = "clk_gpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_npll: pll-clk@0040 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0040 0x10>; - mode-reg = <0x0050 14>; - status-reg = <0x0284 9>; - clocks = <&xin24m>; - clock-output-names = "clk_npll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - /* Select control regs */ - clk_sel_cons { - compatible = "rockchip,rk-sel-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_sel_con0: sel-con@0060 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0060 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_core_m0: aclk_core_m0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 4>; - clocks = <&clk_core>; - clock-output-names = "aclk_core_m0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_core_mp: aclk_core_mp_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <4 4>; - clocks = <&clk_core>; - clock-output-names = "aclk_core_mp"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - clk_core_div: clk_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_core>; - clock-output-names = "clk_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - }; - - /* reg[14:13]: reserved */ - - clk_core: clk_core_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_apll>, <&clk_gates0 2>; - clock-output-names = "clk_core"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con1: sel-con@0064 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0064 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_bus: aclk_bus_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 3>; - clocks = <&aclk_bus_src_div>; - clock-output-names = "aclk_bus"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_bus_src_div: aclk_bus_src_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <3 5>; - clocks = <&aclk_bus_src>; - clock-output-names = "aclk_bus_src"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - hclk_bus: hclk_bus_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_bus>; - clock-output-names = "hclk_bus"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x3 4>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[11:10]: reserved */ - - pclk_bus: pclk_bus_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 3>; - clocks = <&aclk_bus>; - clock-output-names = "pclk_bus"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_bus_src: aclk_bus_src_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - /*clocks = <&clk_gates0 11>, <&clk_gates0 10>; FIXME*/ - clock-output-names = "aclk_bus_src"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con2: sel-con@0068 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0068 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_tsadc: clk_tsadc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&xin32k>; - clock-output-names = "clk_tsadc"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7:6]: reserved */ - - testout_div: testout_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&dummy>; - clock-output-names = "testout_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[15:13]: reserved */ - }; - - clk_sel_con3: sel-con@006c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x006c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart4_div: clk_uart4_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&uart_pll_mux>; - clock-output-names = "clk_uart4_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart4: uart4_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>, <&dummy>; - clock-output-names = "clk_uart4"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[15:10]: reserved */ - - }; - - clk_sel_con4: sel-con@0070 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - i2s_pll_div: i2s_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_i2s_pll>; - clock-output-names = "clk_i2s_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[7]: reserved */ - - clk_i2s: i2s_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>; - clock-output-names = "clk_i2s"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[11:10]: reserved */ - - clk_i2s_out: i2s_outclk_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 1>; - clocks = <&clk_i2s>, <&xin12m>; - clock-output-names = "clk_i2s_out"; - #clock-cells = <0>; - }; - - /* reg[14:13]: reserved */ - - clk_i2s_pll: i2s_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_i2s_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con5: sel-con@0074 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_div: spdif_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spdif_pll>; - clock-output-names = "spdif_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_spdif: spdif_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>, <&dummy>; - clock-output-names = "clk_spdif"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[14:10]: reserved */ - - clk_spdif_pll: spdif_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_spdif_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con6: sel-con@0078 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_isp_div: clk_isp_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&clk_isp>; - clock-output-names = "clk_isp"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_isp: clk_isp_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "clk_isp"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_isp_jpe_div: clk_isp_jpe_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 6>; - clocks = <&clk_isp_jpe>; - clock-output-names = "clk_isp_jpe"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_isp_jpe: clk_isp_jpe_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "clk_isp_jpe"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con7: sel-con@007c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x007c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart4_frac: uart4_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart4_div>; - clock-output-names = "uart4_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con8: sel-con@0080 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0080 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - i2s_frac: i2s_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_i2s_pll>; - clock-output-names = "i2s_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con9: sel-con@0084 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0084 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_frac: spdif_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&spdif_div>; - clock-output-names = "spdif_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con10: sel-con@0088 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0088 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_peri_div: aclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_peri>; - clock-output-names = "aclk_peri"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[7:5]: reserved */ - - hclk_peri: hclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_peri>; - clock-output-names = "hclk_peri"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x2 4>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[11:10]: reserved */ - - pclk_peri: pclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 2>; - clocks = <&aclk_peri>; - clock-output-names = "pclk_peri"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x2 4 - 0x3 8>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[14]: reserved */ - - aclk_peri: aclk_peri_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "aclk_peri"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con11: sel-con@008c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x008c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sdmmc_div: clk_sdmmc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&clk_sdmmc>; - clock-output-names = "clk_sdmmc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_sdmmc: clk_sdmmc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_sdmmc"; - #clock-cells = <0>; - }; - - ehci1phy_12m_div: ehci1phy_12m_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 6>; - clocks = <&ehci1phy_480m>; - clock-output-names = "ehci1phy_12m_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con12: sel-con@0090 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0090 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sdio0_div: clk_sdio0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&clk_sdio0>; - clock-output-names = "clk_sdio0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_sdio0: clk_sdio0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_sdio0"; - #clock-cells = <0>; - }; - - clk_emmc_div: clk_emmc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 6>; - clocks = <&clk_emmc>; - clock-output-names = "clk_emmc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_emmc: clk_emmc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_emmc"; - #clock-cells = <0>; - }; - }; - - clk_sel_con13: sel-con@0094 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0094 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart0_pll_div: clk_uart0_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart0_pll>; - clock-output-names = "clk_uart0_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[7]: reserved */ - - clk_uart0: uart0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>; - clock-output-names = "clk_uart0"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[10]: reserved */ - - usbphy_480m: usbphy_480m_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <11 2>; - clocks = <&otgphy1_480m>, <&otgphy2_480m>, <&otgphy0_480m>; - clock-output-names = "usbphy_480m"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - #clock-init-cells = <1>; - }; - - clk_uart0_pll: clk_uart0_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <13 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>; - clock-output-names = "clk_uart0_pll"; - #clock-cells = <0>; - }; - - uart_pll_mux: uart_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "uart_pll_mux"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con14: sel-con@0098 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0098 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart1_div: clk_uart1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&uart_pll_mux>; - clock-output-names = "clk_uart1_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart1: uart1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>; - clock-output-names = "clk_uart1"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[15:10]: reserved */ - }; - - clk_sel_con15: sel-con@009c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x009c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart2_div: clk_uart2_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&uart_pll_mux>; - clock-output-names = "clk_uart2_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart2: uart2_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>; - clock-output-names = "clk_uart2"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[15:10]: reserved */ - }; - - clk_sel_con16: sel-con@00a0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart3_div: clk_uart3_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&uart_pll_mux>; - clock-output-names = "clk_uart3_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_uart3: uart3_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>; - clock-output-names = "clk_uart3"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[15:10]: reserved */ - }; - - clk_sel_con17: sel-con@00a4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart0_frac: uart0_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart0_pll>; - clock-output-names = "uart0_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con18: sel-con@00a8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart1_frac: uart1_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart1_div>; - clock-output-names = "uart1_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con19: sel-con@00ac { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00ac 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart2_frac: uart2_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart2_div>; - clock-output-names = "uart2_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con20: sel-con@00b0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart3_frac: uart3_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart3_div>; - clock-output-names = "uart3_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con21: sel-con@00b4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_mac_pll: clk_mac_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&clk_npll>, <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_mac_pll"; - #clock-cells = <0>; - }; - - /* reg[3:2]: reserved */ - - clk_mac: clk_mac_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <4 1>; - clocks = <&clk_mac_pll>, <&gmac_clkin>; - clock-output-names = "clk_mac"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - #clock-init-cells = <1>; - }; - - /* reg[7:5]: reserved */ - - clk_mac_pll_div: clk_mac_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_mac_pll>; - clock-output-names = "clk_mac_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[15:13]: reserved */ - }; - - clk_sel_con22: sel-con@00b8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_hsadc_pll: clk_hsadc_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_hsadc_pll"; - #clock-cells = <0>; - }; -/* - wifi_pll_mux: wifi_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <1 1>; - clocks = <&>, <&>; - clock-output-names = "wifi_pll_mux"; - #clock-cells = <0>; - }; -*/ - - /* reg[3:2]: reserved */ - - clk_hsadc_out: clk_hsadc_out { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <4 1>; - clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>; - clock-output-names = "clk_hsadc_out"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[6:5]: reserved */ - - clk_hsadc: clk_hsadc { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>; - clock-output-names = "clk_hsadc"; - #clock-cells = <0>; - }; - - clk_hsadc_pll_div: clk_hsadc_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&clk_hsadc_pll>; - clock-output-names = "clk_hsadc_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - }; -/* - clk_sel_con23: sel-con@00bc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00bc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - wifi_frac: wifi_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&>; - clock-output-names = "wifi_frac"; - / numerator denominator / - rockchip,bits = <0 32>; - rockchip,clkops-idx = - <>; - #clock-cells = <0>; - }; - }; -*/ - - clk_sel_con24: sel-con@00c0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - /* reg[7:0]: reserved */ - - clk_saradc: clk_saradc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&xin24m>; - clock-output-names = "clk_saradc"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - }; - - clk_sel_con25: sel-con@00c4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_spi0_div: clk_spi0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spi0>; - clock-output-names = "clk_spi0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_spi0: clk_spi0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_spi0"; - #clock-cells = <0>; - }; - - clk_spi1_div: clk_spi1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 7>; - clocks = <&clk_spi1>; - clock-output-names = "clk_spi1"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_spi1: clk_spi1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_spi1"; - #clock-cells = <0>; - }; - }; - - clk_sel_con26: sel-con@00c8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - ddr_div: ddr_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 2>; - clocks = <&clk_ddr>; - clock-output-names = "clk_ddr"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x3 4>; - #clock-cells = <0>; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - rockchip,clkops-idx = ; - }; - - clk_ddr: ddr_clk_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <2 1>; - clocks = <&clk_dpll>, <&clk_gpll>; - clock-output-names = "clk_ddr"; - #clock-cells = <0>; - }; - - /* reg[5:3]: reserved */ - - clk_crypto: crypto_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <6 2>; - clocks = <&aclk_bus>; - clock-output-names = "clk_crypto"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_cif_pll: clk_cif_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_cif_pll"; - #clock-cells = <0>; - }; - - clk_cif_out_div: clk_cif_out_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <9 5>; - clocks = <&clk_cif_out>; - clock-output-names = "clk_cif_out"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[14]: reserved */ - - clk_cif_out: clk_cif_out_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cif_pll>, <&xin24m>; - clock-output-names = "clk_cif_out"; - #clock-cells = <0>; - }; - }; - - clk_sel_con27: sel-con@00cc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00cc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - dclk_lcdc0: dclk_lcdc0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "dclk_lcdc0"; - #clock-cells = <0>; - }; - - /* reg[7:2]: reserved */ - - dclk_lcdc0_div: dclk_lcdc0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&dclk_lcdc0>; - clock-output-names = "dclk_lcdc0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - }; - - clk_sel_con28: sel-con@00d0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00d0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_edp_div: clk_edp_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 6>; - clocks = <&clk_edp>; - clock-output-names = "clk_edp"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_edp: clk_edp_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "clk_edp"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - hclk_vio: hclk_vio_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_gates15 11>; - clock-output-names = "hclk_vio"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[14:13]: reserved */ - - clk_edp_24m: edp_24m_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&edp_24m_clkin>, <&xin24m>; - clock-output-names = "clk_edp_24m"; - #clock-cells = <0>; - }; - }; - - clk_sel_con29: sel-con@00d4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00d4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - ehci1phy_480m: ehci1phy_480m_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "ehci1phy_480m"; - #clock-cells = <0>; - }; - - ehci1phy_12m: ehci1phy_12m_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <2 1>; - clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>; - clock-output-names = "ehci1phy_12m"; - #clock-cells = <0>; - }; - - clkin_isp: clkin_isp { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <3 1>; - clocks = <&clk_gates16 3>, <&pclkin_isp_inv>; - clock-output-names = "clkin_isp"; - #clock-cells = <0>; - }; - - clkin_cif: clkin_cif { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <4 1>; - clocks = <&clk_gates16 0>, <&pclkin_cif_inv>; - clock-output-names = "clkin_cif"; - #clock-cells = <0>; - }; - - /* reg[5]: reserved */ - - dclk_lcdc1: dclk_lcdc1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "dclk_lcdc1"; - #clock-cells = <0>; - }; - - dclk_lcdc1_div: dclk_lcdc1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&dclk_lcdc1>; - clock-output-names = "dclk_lcdc1"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - }; - - clk_sel_con30: sel-con@00d8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00d8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_rga_div: aclk_rga_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_rga>; - clock-output-names = "aclk_rga"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[5]: reserved */ - - aclk_rga: aclk_rga_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "aclk_rga"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_rga_div: clk_rga_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_rga>; - clock-output-names = "clk_rga"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[13]: reserved */ - - clk_rga: clk_rga_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "clk_rga"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con31: sel-con@00dc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00dc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_vio0_div: aclk_vio0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_vio0>; - clock-output-names = "aclk_vio0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[5]: reserved */ - - aclk_vio0: aclk_vio0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "aclk_vio0"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_vio1_div: aclk_vio1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_vio1>; - clock-output-names = "aclk_vio1"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[13]: reserved */ - - aclk_vio1: aclk_vio1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "aclk_vio1"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con32: sel-con@00e0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00e0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_vepu_div: clk_vepu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_vepu>; - clock-output-names = "clk_vepu"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[5]: reserved */ - - clk_vepu: clk_vepu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "clk_vepu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_vdpu_div: clk_vdpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_vdpu>; - clock-output-names = "clk_vdpu"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[13]: reserved */ - - clk_vdpu: clk_vdpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "clk_vdpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con33: sel-con@00e4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00e4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - pclk_pd_pmu: pclk_pd_pmu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_gpll>; - clock-output-names = "pclk_pd_pmu"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[7:5]: reserved */ - - pclk_pd_alive: pclk_pd_alive { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_gpll>; - clock-output-names = "pclk_pd_alive"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15:13]: reserved */ - }; - - clk_sel_con34: sel-con@00e8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00e8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_gpu_div: clk_gpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_gpu>; - clock-output-names = "clk_gpu"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[5]: reserved */ - - clk_gpu: clk_gpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>; - clock-output-names = "clk_gpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_sdio1_div: clk_sdio1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 6>; - clocks = <&clk_sdio1>; - clock-output-names = "clk_sdio1"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_sdio1: clk_sdio1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>; - clock-output-names = "clk_sdio1"; - #clock-cells = <0>; - }; - }; - - clk_sel_con35: sel-con@00ec { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00ec 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_tsp_div: clk_tsp_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_tsp>; - clock-output-names = "clk_tsp"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[5]: reserved */ - - clk_tsp: clk_tsp_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "clk_tsp"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_tspout_div: clk_tspout_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_tspout>; - clock-output-names = "clk_tspout"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[13]: reserved */ - - clk_tspout: clk_tspout_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>; - clock-output-names = "clk_tspout"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con36: sel-con@00f0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00f0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_core0: clk_core0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 3>; - clocks = <&clk_core>; - clock-output-names = "clk_core0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* reg[3]: reserved */ - - clk_core1: clk_core1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <4 3>; - clocks = <&clk_core>; - clock-output-names = "clk_core1"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* reg[7]: reserved */ - - clk_core2: clk_core2_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 3>; - clocks = <&clk_core>; - clock-output-names = "clk_core2"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* reg[11]: reserved */ - - clk_core3: clk_core3_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 3>; - clocks = <&clk_core>; - clock-output-names = "clk_core3"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* reg[15]: reserved */ - }; - - clk_sel_con37: sel-con@00f4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00f4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_l2ram: clk_l2ram_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 3>; - clocks = <&clk_core>; - clock-output-names = "clk_l2ram"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* reg[3]: reserved */ - - atclk_core: atclk_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <4 5>; - clocks = <&clk_core>; - clock-output-names = "atclk_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - pclk_dbg_src: pclk_core_dbg_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <9 5>; - clocks = <&clk_core>; - clock-output-names = "pclk_dbg_src"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* reg[15:14]: reserved */ - }; - - clk_sel_con38: sel-con@00f8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00f8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_nandc0_div: clk_nandc0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_nandc0>; - clock-output-names = "clk_nandc0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[6:5]: reserved */ - - clk_nandc0: clk_nandc0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_nandc0"; - #clock-cells = <0>; - }; - - clk_nandc1_div: clk_nandc1_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_nandc1>; - clock-output-names = "clk_nandc1"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* reg[14:13]: reserved */ - - clk_nandc1: clk_nandc1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_nandc1"; - #clock-cells = <0>; - }; - }; - - clk_sel_con39: sel-con@00fc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00fc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_spi2_div: clk_spi2_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spi2>; - clock-output-names = "clk_spi2"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_spi2: clk_spi2_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&dummy_cpll>, <&clk_gpll>; - clock-output-names = "clk_spi2"; - #clock-cells = <0>; - }; - - aclk_hevc_div: aclk_hevc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_hevc>; - clock-output-names = "aclk_hevc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[13]: reserved */ - - aclk_hevc: aclk_hevc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "aclk_hevc"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con40: sel-con@0100 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0100 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_8ch_div: spdif_8ch_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spdif_pll>; - clock-output-names = "spdif_8ch_div"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* reg[7]: reserved */ - - clk_spdif_8ch: spdif_8ch_clk_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>; - clock-output-names = "clk_spdif_8ch"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[11:10]: reserved */ - - hclk_hevc: hclk_hevc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 2>; - clocks = <&aclk_hevc>; - clock-output-names = "hclk_hevc"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* reg[15:14]: reserved */ - }; - - clk_sel_con41: sel-con@0104 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0104 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_8ch_frac: spdif_8ch_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&spdif_8ch_div>; - clock-output-names = "spdif_8ch_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con42: sel-con@0108 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0108 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_hevc_cabac_div: clk_hevc_cabac_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_hevc_cabac>; - clock-output-names = "clk_hevc_cabac"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[5]: reserved */ - - clk_hevc_cabac: clk_hevc_cabac_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "clk_hevc_cabac"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_hevc_core_div: clk_hevc_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_hevc_core>; - clock-output-names = "clk_hevc_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* reg[13]: reserved */ - - clk_hevc_core: clk_hevc_core_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; - clock-output-names = "clk_hevc_core"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - }; - - - /* Gate control regs */ - clk_gate_cons { - compatible = "rockchip,rk-gate-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges ; - - clk_gates0: gate-clk@0160 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0160 0x4>; - clocks = - <&dummy>, <&clk_apll>, - <&clk_gpll>, <&aclk_bus>, - - <&hclk_bus>, <&pclk_bus>, - <&dummy>, <&aclk_bus>, - - <&clk_dpll>, <&clk_gpll>, - <&clk_gpll>, <&clk_cpll>, - - <&xin24m>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "reserved", "reserved", /* do not use bit1 = "core_apll" */ - "clk_arm_gpll", "g_aclk_bus", - - "hclk_bus", "pclk_bus", - "reserved", "aclk_bus_2pmu", - - "reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/ - "reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/ - - "clk_acc_efuse", "reserved", - "reserved", "reserved"; - rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@0164 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0164 0x4>; - clocks = - <&xin24m>, <&xin24m>, - <&xin24m>, <&xin24m>, - - <&xin24m>, <&xin24m>, - <&dummy>, <&dummy>, - - <&clk_uart0_pll>, <&uart0_frac>, - <&clk_uart1_div>, <&uart1_frac>, - - <&clk_uart2_div>, <&uart2_frac>, - <&clk_uart3_div>, <&uart3_frac>; - - clock-output-names = - "clk_timer0", "clk_timer1", - "clk_timer2", "clk_timer3", - - "clk_timer4", "clk_timer5", - "reserved", "reserved", - - "clk_uart0_pll", "uart0_frac", - "clk_uart1_div", "uart1_frac", - - "clk_uart2_div", "uart2_frac", - "clk_uart3_div", "uart3_frac"; - - rockchip,suspend-clkgating-setting=<0x0 0x0>; - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@0168 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0168 0x4>; - clocks = - <&aclk_peri>, <&aclk_peri>, - <&hclk_peri>, <&pclk_peri>, - - <&dummy>, <&clk_mac_pll>, - <&clk_hsadc_pll>, <&clk_tsadc>, - - <&clk_saradc>, <&clk_spi0>, - <&clk_spi1>, <&clk_spi2>, - - <&clk_uart4_div>, <&uart4_frac>, - <&dummy>, <&dummy>; - - clock-output-names = - "aclk_peri", "reserved", /*"g_aclk_periph",*/ - "hclk_peri", "pclk_peri", - - "reserved", "clk_mac_pll", - "clk_hsadc_pll", "clk_tsadc", - - "clk_saradc", "clk_spi0", - "clk_spi1", "clk_spi2", - - "clk_uart4_div", "uart4_frac", - "reserved", "reserved"; - rockchip,suspend-clkgating-setting=<0x000f 0x000f>; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@016c { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x016c 0x4>; - clocks = - <&aclk_vio0>, <&dclk_lcdc0>, - <&aclk_vio1>, <&dclk_lcdc1>, - - <&clk_rga>, <&aclk_rga>, - <&ehci1phy_480m>, <&clk_cif_pll>, - - <&dummy>, <&clk_vepu>, - <&dummy>, <&clk_vdpu>, - - <&clk_edp_24m>, <&clk_edp>, - <&clk_isp>, <&clk_isp_jpe>; - - clock-output-names = - "aclk_vio0", "dclk_lcdc0", - "aclk_vio1", "dclk_lcdc1", - - "clk_rga", "aclk_rga", - "ehci1phy_480m", "clk_cif_pll", - - /*Not use hclk_vpu_gate tmp, fixme*/ - "reserved", "clk_vepu", - "reserved", "clk_vdpu", - - "clk_edp_24m", "clk_edp", - "clk_isp", "clk_isp_jpe"; - rockchip,suspend-clkgating-setting=<0x0000 0x0000>; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@0170 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0170 0x4>; - clocks = - <&clk_i2s_out>, <&clk_i2s_pll>, - <&i2s_frac>, <&clk_i2s>, - - <&spdif_div>, <&spdif_frac>, - <&clk_spdif>, <&spdif_8ch_div>, - - <&spdif_8ch_frac>, <&clk_spdif_8ch>, - <&clk_tsp>, <&clk_tspout>, - - <&clk_ddr>, <&clk_ddr>, - <&jtag_clkin>, <&dummy>; - - clock-output-names = - "clk_i2s_out", "clk_i2s_pll", - "i2s_frac", "clk_i2s", - - "spdif_div", "spdif_frac", - "clk_spdif", "spdif_8ch_div", - - "spdif_8ch_frac", "clk_spdif_8ch", - "clk_tsp", "clk_tspout", - - /* Not use these ddr gates */ - "reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/ - "clk_jtag", "reserved"; /*"testclk_gate_en";*/ - - rockchip,suspend-clkgating-setting=<0xf000 0xf000>; - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@0174 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0174 0x4>; - clocks = - <&clk_mac>, <&clk_mac>, - <&clk_mac>, <&clk_mac>, - - <&clk_crypto>, <&clk_nandc0>, - <&clk_nandc1>, <&clk_gpu>, - - <&pclk_pd_pmu>, <&xin24m>, - <&xin24m>, <&xin32k>, - - <&xin24m>, <&xin24m>, - <&usbphy_480m>, <&xin24m>; - - clock-output-names = - "g_clk_mac_rx", "g_clk_mac_tx", - "g_clk_mac_ref", "g_mac_refout", - - "clk_crypto", "clk_nandc0", - "clk_nandc1", "clk_gpu", - - "pclk_pd_pmu", "g_clk_pvtm_core", - "g_clk_pvtm_gpu", "g_hdmi_cec_clk", - - "g_hdmi_hdcp_clk", "g_ps2c_clk", - "usbphy_480m", "g_mipidsi_24m"; - rockchip,suspend-clkgating-setting=<0x0100 0x0100>; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@0178 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0178 0x4>; - clocks = - <&hclk_peri>, <&pclk_peri>, - <&aclk_peri>, <&aclk_peri>, - - <&pclk_peri>, <&pclk_peri>, - <&pclk_peri>, <&pclk_peri>, - - <&pclk_peri>, <&pclk_peri>, - <&dummy>, <&pclk_peri>, - - <&pclk_peri>, <&pclk_peri>, - <&pclk_peri>, <&pclk_peri>; - - clock-output-names = - "g_hp_matrix", "g_pp_axi_matrix", - "g_ap_axi_matrix", "g_aclk_dmac2", - - "g_pclk_spi0", "g_pclk_spi1", - "g_pclk_spi2", "g_pclk_ps2c", - - "g_pclk_uart0", "g_pclk_uart1", - "reserved", "g_pclk_uart3", - - "g_pclk_uart4", "g_pclk_i2c1", - "g_pclk_i2c3", "g_pclk_i2c4"; - rockchip,suspend-clkgating-setting=<0x0003 0x0003>; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@017c { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x017c 0x4>; - clocks = - <&pclk_peri>, <&pclk_peri>, - <&pclk_peri>, <&pclk_peri>, - - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&hclk_peri>, - - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&aclk_peri>, - - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&hclk_peri>; - - clock-output-names = - "g_pclk_i2c5", "g_pclk_saradc", - "g_pclk_tsadc", "g_pclk_sim", - - "g_hclk_otg0", "g_pmu_hclk_otg0", - "g_hclk_host0", "g_hclk_host1", - - "g_hclk_ehci1", "g_hclk_usb_peri", - "g_hp_ahb_arbi", "g_aclk_peri_niu", - - "g_h_emem_peri", "g_hclk_mem_peri", - "g_hclk_nandc0", "g_hclk_nandc1"; - rockchip,suspend-clkgating-setting=<0x0c00 0xc000>; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@0180 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0180 0x4>; - clocks = - <&aclk_peri>, <&pclk_peri>, - <&aclk_peri>, <&hclk_peri>, - - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&hclk_peri>, - - <&hclk_peri>, <&hsadc_0_tsp>, - <&hsadc_1_tsp>, <&io_27m_in>, - - <&aclk_peri>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_aclk_gmac", "g_pclk_gmac", - "g_hclk_gps", "g_hclk_sdmmc", - - "g_hclk_sdio0", "g_hclk_sdio1", - "g_hclk_emmc", "g_hclk_hsadc", - - "g_hclk_tsp", "g_hsadc_0_tsp", - "g_hsadc_1_tsp", "g_clk_27m_tsp", - - "g_aclk_peri_mmu", "reserved", - "reserved", "reserved"; - - rockchip,suspend-clkgating-setting=<0x0000 0x0000>; - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@0184 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0184 0x4>; - clocks = - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/ - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - rockchip,suspend-clkgating-setting=<0x0 0x0>; - - #clock-cells = <1>; - }; - - clk_gates10: gate-clk@0188 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0188 0x4>; - clocks = - <&pclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&pclk_bus>, - - <&aclk_bus>, <&aclk_bus>, - <&aclk_bus>, <&aclk_bus>, - - <&hclk_bus>, <&hclk_bus>, - <&hclk_bus>, <&hclk_bus>, - - <&aclk_bus>, <&aclk_bus>, - <&pclk_bus>, <&pclk_bus>; - - clock-output-names = - "g_pclk_pwm", "g_pclk_timer", - "g_pclk_i2c0", "g_pclk_i2c2", - - "g_aclk_intmem", "g_clk_intmem0", - "g_clk_intmem1", "g_clk_intmem2", - - "g_hclk_i2s", "g_hclk_rom", - "g_hclk_spdif", "g_h_spdif_8ch", - - "g_aclk_dmac1", "g_aclk_strc_sys", - "reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/ - - //rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating - rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol - - #clock-cells = <1>; - }; - - clk_gates11: gate-clk@018c { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x018c 0x4>; - clocks = - <&pclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&pclk_bus>, - - <&dummy>, <&dummy>, - <&aclk_bus>, <&hclk_bus>, - - <&aclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&pclk_bus>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/ - "g_p_efuse_1024", "g_pclk_tzpc", - - "reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/ - "g_aclk_crypto", "g_hclk_crypto", - - "g_aclk_ccp", "g_pclk_uart2", - "g_p_efuse_256", "g_pclk_rkpwm", - - "reserved", "reserved", - "reserved", "reserved"; - rockchip,suspend-clkgating-setting=<0x0033 0x0033>; - - #clock-cells = <1>; - }; - - clk_gates12: gate-clk@0190 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0190 0x4>; - clocks = - <&clk_core0>, <&clk_core1>, - <&clk_core2>, <&clk_core3>, - - <&clk_l2ram>, <&aclk_core_m0>, - <&aclk_core_mp>, <&atclk_core>, - - <&pclk_dbg_src>, <&pclk_dbg_src>, - <&pclk_dbg_src>, <&pclk_dbg_src>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "clk_core0", "clk_core1", - "clk_core2", "clk_core3", - - "clk_l2ram", "aclk_core_m0", - "aclk_core_mp", "atclk_core", - - "pclk_dbg_src", "g_dbg_core_clk", - "g_cs_dbg_clk", "g_pclk_core_niu", - - "reserved", "reserved", - "reserved", "reserved"; - rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>; - - #clock-cells = <1>; - }; - - clk_gates13: gate-clk@0194 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0194 0x4>; - clocks = - <&clk_sdmmc>, <&clk_sdio0>, - <&clk_sdio1>, <&clk_emmc>, - - <&xin24m>, <&xin24m>, - <&xin24m>, <&xin32k>, - - <&aclk_bus_src>, <&xin12m>, - <&xin24m>, <&xin24m>, - - <&dummy>, <&aclk_hevc>, - <&clk_hevc_cabac>, <&clk_hevc_core>; - - clock-output-names = - "clk_sdmmc", "clk_sdio0", - "clk_sdio1", "clk_emmc", - - "clk_otgphy0", "clk_otgphy1", - "clk_otgphy2", "clk_otg_adp", - - "g_clk_c2c_host", "g_clk_ehci1_12m", - "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1", - - "g_clk_wifi", "aclk_hevc", - "clk_hevc_cabac", "clk_hevc_core"; - rockchip,suspend-clkgating-setting=<0x0 0x0>; - - #clock-cells = <1>; - }; - - clk_gates14: gate-clk@0198 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0198 0x4>; - clocks = - <&dummy>, <&pclk_pd_alive>, - <&pclk_pd_alive>, <&pclk_pd_alive>, - - <&pclk_pd_alive>, <&pclk_pd_alive>, - <&pclk_pd_alive>, <&pclk_pd_alive>, - - <&pclk_pd_alive>, <&dummy>, - <&dummy>, <&pclk_pd_alive>, - - <&pclk_pd_alive>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "reserved", "g_pclk_gpio1", - "g_pclk_gpio2", "g_pclk_gpio3", - - "g_pclk_gpio4", "g_pclk_gpio5", - "g_pclk_gpio6", "g_pclk_gpio7", - - "g_pclk_gpio8", "reserved", - "reserved", "g_pclk_grf", - - "g_p_alive_niu", "reserved", - "reserved", "reserved"; - //rockchip,suspend-clkgating-setting=<0xffff 0xffff>; - - rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>; - - #clock-cells = <1>; - }; - - clk_gates15: gate-clk@019c { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x019c 0x4>; - clocks = - <&aclk_rga>, <&hclk_vio>, - <&clk_gates15 11>, <&hclk_vio>, - - <&dummy>, <&clk_gates15 11>, - <&hclk_vio>, <&clk_gates15 12>, - - <&hclk_vio>, <&dummy>, - <&dummy>, <&aclk_vio0>, - - <&aclk_vio1>, <&aclk_rga>, - <&clk_gates15 11>, <&hclk_vio>; - - clock-output-names = - "reserved", /*"g_aclk_rga"*/ "g_hclk_rga", - "g_aclk_iep", "g_hclk_iep", - - "g_aclk_lcdc_iep", "g_aclk_lcdc0", - "g_hclk_lcdc0", "g_aclk_lcdc1", - - "g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */ - "reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu", - - "g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/ - "g_aclk_vip", "g_hclk_vip"; - rockchip,suspend-clkgating-setting=<0x0 0x0>; - - #clock-cells = <1>; - }; - - clk_gates16: gate-clk@01a0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x01a0 0x4>; - clocks = - <&pclkin_cif>, <&hclk_vio>, - <&clk_gates15 12>, <&pclkin_isp>, - - <&hclk_vio>, <&hclk_vio>, - <&hclk_vio>, <&hclk_vio>, - - <&hclk_vio>, <&hclk_vio>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_pclkin_cif", "g_hclk_isp", - "g_aclk_isp", "g_pclkin_isp", - - "g_p_mipi_dsi0", "g_p_mipi_dsi1", - "g_p_mipi_csi", "g_pclk_lvds_phy", - - "g_pclk_edp_ctrl", "g_p_hdmi_ctrl", - "reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */ - - "reserved", "reserved", - "reserved", "reserved"; - rockchip,suspend-clkgating-setting=<0x0 0x0>; - - #clock-cells = <1>; - }; - - clk_gates17: gate-clk@01a4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x01a4 0x4>; - clocks = - <&pclk_pd_pmu>, <&pclk_pd_pmu>, - <&pclk_pd_pmu>, <&pclk_pd_pmu>, - - <&pclk_pd_pmu>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_pclk_pmu", "g_pclk_intmem1", - "g_pclk_pmu_niu", "g_pclk_sgrf", - - "g_pclk_gpio0", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - rockchip,suspend-clkgating-setting=<0x01f 0x01f>; - - #clock-cells = <1>; - }; - - clk_gates18: gate-clk@01a8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x01a8 0x4>; - clocks = - <&clk_gpu>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "reserved", /*"g_aclk_gpu",*/ "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - - rockchip,suspend-clkgating-setting=<0x0 0x0>; - #clock-cells = <1>; - }; - - }; - }; - }; -};