From d883eb7e3cc5b0f9a92080f47cd6b8a8c1935b67 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 29 May 2019 15:40:13 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3326-w7: set VIF_PLL and SCL_PLL clock parents to LCDC0_CLK Change-Id: I71fce70e464771278719affb8f2573d0dbda1a27 Signed-off-by: Wyon Bi --- .../boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi-rgb.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi-rgb.dts b/arch/arm64/boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi-rgb.dts index 13a7c6bedaea..8150922c6703 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi-rgb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi-rgb.dts @@ -97,8 +97,6 @@ pinctrl-0 = <&i2s1_2ch_mclk>; clocks = <&cru SCLK_I2S1_OUT>; clock-names = "clkin"; - assigned-clocks = <&cru SCLK_I2S1_OUT>; - assigned-clock-rates = <12000000>; reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; status = "okay"; @@ -112,8 +110,8 @@ <&clock VIF0_PRE_CLK>, <&clock CODEC_CLK>, <&clock DITHER_CLK>; - assigned-clock-parents = <&cru SCLK_I2S1_OUT>, - <&cru SCLK_I2S1_OUT>, + assigned-clock-parents = <&clock LCDC0_CLK>, + <&clock LCDC0_CLK>, <&clock SCALER_PLL_CLK>, <&clock VIF_PLL_CLK>, <&cru SCLK_I2S1_OUT>,