From d89acabf0693867bbd23386ccee95399539fec7f Mon Sep 17 00:00:00 2001
From: Tao Huang <huangtao@rock-chips.com>
Date: Fri, 12 Nov 2021 15:33:29 +0800
Subject: [PATCH] Revert "clk: rockchip: Temporarily fix for rk3588 pll"

This reverts commit fb7d7606a1069afb75653f73412fead2a4e2aaf2.

Change-Id: I232636a08a2c034df5ac41d1f628ad55e4e59e36
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
---
 drivers/clk/rockchip/clk-pll.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 34056e83480e..3bd161d066ec 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1268,9 +1268,6 @@ static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
 	u32 pllcon;
 	int ret;
 
-	for (ret = 0; ret < 1000; ret++)
-		asm("nop");
-	return 0;
 	/*
 	 * Lock time typical 250, max 500 input clock cycles @24MHz
 	 * So define a very safe maximum of 1000us, meaning 24000 cycles.