From d8f8857b7e03e043f49ebf17dc8a4000bbc09524 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 5 Jan 2021 11:33:49 +0800 Subject: [PATCH] clk: rockchip: rk3568: add READ_ONLY flag for clk_gpu clk_gpu is not allow to set rate, just read only. Signed-off-by: Elaine Zhang Change-Id: I59b31b059cfe941104765c066a0c678b1ca50312 --- drivers/clk/rockchip/clk-rk3568.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index d95f34b8ec2a..b9f420110f9b 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -560,10 +560,10 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { /* PD_GPU */ COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(2), 0, GFLAGS), MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(6), 11, 1, MFLAGS), + RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY), DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, RK3568_CLKSEL_CON(6), 8, 2, DFLAGS), DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0,