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deintlace: register setting default disable hdr2 [1/1]

Browse Source 
PD#SWPL-16107

Problem:
cpu_after_eq(MESON_CPU_MAJOR_ID_TM2)default disable hdr2

Solution:
default disable hdr2,from VLSI feijun
DI_HDR2_HIST_CTRL, 0x5510
DI_HDR2_HIST_H_START_END, 0x10000
DI_HDR2_HIST_V_START_END, 0x0

Verify:
verify on x301_t96x2

Change-Id: Ib646111fb866570a75775534e446807f1e3b4a91
Signed-off-by: qianqian.cai <qianqian.cai@amlogic.com>
This commit is contained in:
qianqian.cai
2019-11-01 18:16:16 +08:00
committed by Tao Zeng
parent 238dc24e90
commit db6ee17007
4 changed files with 18 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -7122,6 +7122,7 @@ static void di_reg_process_irq(void)
DI_Wr(DI_CLKG_CTRL, 0xfef60001);
/* nr/blend0/ei0/mtn0 clock gate */
}
di_hdr2_hist_init();
if (di_printk_flag & 2)
di_printk_flag = 1;

9
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -3367,6 +3367,15 @@ void diwr_set_power_control(unsigned char enable)
enable?VPU_MEM_POWER_ON:VPU_MEM_POWER_DOWN);
}
void di_hdr2_hist_init(void)
{
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TM2)) {
RDMA_WR(DI_HDR2_HIST_CTRL, 0x5510);
RDMA_WR(DI_HDR2_HIST_H_START_END, 0x10000);
RDMA_WR(DI_HDR2_HIST_V_START_END, 0x0);
}
}
void di_top_gate_control(bool top_en, bool mc_en)
{
if (top_en) {

1
drivers/amlogic/media/deinterlace/deinterlace_hw.h
View File

@@ -184,6 +184,7 @@ void di_post_switch_buffer(
);
void di_post_read_reverse_irq(bool reverse,
unsigned char mc_pre_flag, bool mc_enable);
void di_hdr2_hist_init(void);
void di_top_gate_control(bool top_en, bool mc_en);
void di_pre_gate_control(bool enable, bool mc_enable);
void di_post_gate_control(bool gate);

7
drivers/amlogic/media/deinterlace/register.h
View File

@@ -180,6 +180,13 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
#define MCINFWR_Y 0x37f6
#define MCINFWR_CTRL 0x37f7
#define MCINFWR_CAN_SIZE 0x37f8
/* from TM2 new added */
/* DI HDR2 */
#define DI_HDR2_HIST_CTRL 0x37ad
#define DI_HDR2_HIST_H_START_END 0x37ae
#define DI_HDR2_HIST_V_START_END 0x37af
/* DI SCALE */
#define DI_SCO_FIFO_CTRL 0x374e
#define DI_SC_TOP_CTRL 0x374f