From dba7790c2653806ccb842207ba49671af2e8fd63 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Wed, 1 Mar 2023 15:41:54 +0800 Subject: [PATCH] media: rockchip: vicap fixes pclk polarity for rv1106 Fixes: 74aca7167d7d ("media: rockchip: rv1106 vicap support dvp") Signed-off-by: Zefa Chen Change-Id: I521d0f56061486f7db4ebe283382aa69c4f2d5e3 --- drivers/media/platform/rockchip/cif/regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/regs.h b/drivers/media/platform/rockchip/cif/regs.h index 2d913519c85a..fccd0057e425 100644 --- a/drivers/media/platform/rockchip/cif/regs.h +++ b/drivers/media/platform/rockchip/cif/regs.h @@ -1047,10 +1047,10 @@ enum cif_reg_index { #define RV1106_CIF_GRF_VENC_WRAPPER (0x10008) #define RV1106_CIF_PCLK_SINGLE_EDGE (0x00040000) #define RV1106_CIF_PCLK_DUAL_EDGE (0x00040004) -#define RV1106_CIF_PCLK_EDGE_RISING_M0 (0x00020000) -#define RV1106_CIF_PCLK_EDGE_FALLING_M0 (0x00020002) -#define RV1106_CIF_PCLK_EDGE_RISING_M1 (0x00010000) -#define RV1106_CIF_PCLK_EDGE_FALLING_M1 (0x00010001) +#define RV1106_CIF_PCLK_EDGE_RISING_M0 (0x00020002) +#define RV1106_CIF_PCLK_EDGE_FALLING_M0 (0x00020000) +#define RV1106_CIF_PCLK_EDGE_RISING_M1 (0x00010001) +#define RV1106_CIF_PCLK_EDGE_FALLING_M1 (0x00010000) #define RV1106_CIF_GRF_SEL_M0 (0x00010000) #define RV1106_CIF_GRF_SEL_M1 (0x00010001)