From dbd5f3330133dd5c910d18becadd176f38ec7a70 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 29 Nov 2021 15:04:20 +0800 Subject: [PATCH] clk: rockchip: rk3588: Change the clk registration sequence Reduces clock registration time Signed-off-by: Elaine Zhang Change-Id: I9ee110dde6cfcae13fbec6604567c930b709d34b --- drivers/clk/rockchip/clk-rk3588.c | 764 +++++++++++++++--------------- 1 file changed, 382 insertions(+), 382 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 070ecd9b92f2..61765899d61e 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -675,6 +675,117 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { /* fixed */ FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + /* top */ + COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 9, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 10, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 11, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 12, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 13, GFLAGS), + COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 3, GFLAGS), + COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 4, GFLAGS), + COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, + RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 6, GFLAGS), + GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(3), 14, GFLAGS), + GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(4), 3, GFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(5), 0, GFLAGS), + /* bigcore0 */ COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, @@ -750,6 +861,12 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), /* audio */ + COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 1, GFLAGS), GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, RK3588_CLKGATE_CON(7), 12, GFLAGS), GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, @@ -811,12 +928,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(9), 7, GFLAGS), - COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(7), 0, GFLAGS), - COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, - RK3588_CLKGATE_CON(7), 1, GFLAGS), GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, RK3588_CLKGATE_CON(8), 14, GFLAGS), @@ -845,15 +956,15 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(68), 0, GFLAGS), - GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, - RK3588_CLKGATE_CON(68), 2, GFLAGS), COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, RK3588_CLKGATE_CON(68), 3, GFLAGS), - GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, - RK3588_CLKGATE_CON(68), 5, GFLAGS), /* bus */ + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(10), 0, GFLAGS), + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, RK3588_CLKGATE_CON(16), 11, GFLAGS), GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, @@ -955,10 +1066,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(10), 6, GFLAGS), GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, RK3588_CLKGATE_CON(10), 7, GFLAGS), - - COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(10), 0, GFLAGS), GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, RK3588_CLKGATE_CON(10), 3, GFLAGS), @@ -1222,117 +1329,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, RK3588_CLKGATE_CON(70), 10, GFLAGS), - /* top */ - COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 0, GFLAGS), - COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 1, GFLAGS), - COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 2, GFLAGS), - COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 3, GFLAGS), - COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 4, GFLAGS), - COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 5, GFLAGS), - COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 6, GFLAGS), - COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 7, GFLAGS), - COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 8, GFLAGS), - COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 9, GFLAGS), - COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 10, GFLAGS), - COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 11, GFLAGS), - COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 12, GFLAGS), - COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 13, GFLAGS), - COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 14, GFLAGS), - COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, - RK3588_CLKGATE_CON(0), 15, GFLAGS), - COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(1), 10, GFLAGS), - COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, - RK3588_CLKGATE_CON(1), 11, GFLAGS), - COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, - RK3588_CLKGATE_CON(1), 12, GFLAGS), - COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, - RK3588_CLKGATE_CON(1), 13, GFLAGS), - COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, - RK3588_CLKGATE_CON(1), 14, GFLAGS), - COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, - RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3588_CLKGATE_CON(5), 9, GFLAGS), - COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, - RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3588_CLKGATE_CON(5), 10, GFLAGS), - COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, - RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3588_CLKGATE_CON(5), 11, GFLAGS), - COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, - RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3588_CLKGATE_CON(5), 12, GFLAGS), - COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, - RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3588_CLKGATE_CON(5), 13, GFLAGS), - COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, - RK3588_CLKGATE_CON(5), 3, GFLAGS), - COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, - RK3588_CLKGATE_CON(5), 4, GFLAGS), - COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, - RK3588_CLKGATE_CON(5), 5, GFLAGS), - COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, - RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3588_CLKGATE_CON(5), 6, GFLAGS), - GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, - RK3588_CLKGATE_CON(3), 14, GFLAGS), - GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, - RK3588_CLKGATE_CON(4), 3, GFLAGS), - GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, - RK3588_CLKGATE_CON(1), 6, GFLAGS), - GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, - RK3588_CLKGATE_CON(1), 8, GFLAGS), - COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(1), 0, GFLAGS), - COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, - RK3588_CLKGATE_CON(1), 1, GFLAGS), - COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, - RK3588_CLKGATE_CON(1), 2, GFLAGS), - GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, - RK3588_CLKGATE_CON(5), 0, GFLAGS), - /* gpu */ COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(161), 0, 2, MFLAGS, @@ -1370,12 +1366,17 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(26), 3, GFLAGS), GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, RK3588_CLKGATE_CON(26), 4, GFLAGS), - GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, - RK3588_CLKGATE_CON(26), 5, GFLAGS), - GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, - RK3588_CLKGATE_CON(26), 7, GFLAGS), /* npu */ + COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 0, GFLAGS), + COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(29), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 4, GFLAGS), GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, RK3588_CLKGATE_CON(27), 0, GFLAGS), GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, @@ -1404,15 +1405,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(30), 6, GFLAGS), GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, RK3588_CLKGATE_CON(30), 8, GFLAGS), - COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(29), 0, GFLAGS), - COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, - RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(29), 1, GFLAGS), - COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, - RK3588_CLKGATE_CON(29), 4, GFLAGS), GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, RK3588_CLKGATE_CON(29), 6, GFLAGS), COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, @@ -1428,8 +1420,12 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(29), 11, GFLAGS), /* nvm */ - GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, - RK3588_CLKGATE_CON(31), 4, GFLAGS), + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(31), 0, GFLAGS), + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 1, GFLAGS), GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 5, GFLAGS), COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, @@ -1444,16 +1440,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, RK3588_CLKGATE_CON(31), 9, GFLAGS), - GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, - RK3588_CLKGATE_CON(31), 10, GFLAGS), - GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, - RK3588_CLKGATE_CON(31), 11, GFLAGS), - COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(31), 0, GFLAGS), - COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(31), 1, GFLAGS), /* php */ COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, @@ -1469,8 +1455,19 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3588_CLKGATE_CON(35), 6, GFLAGS), + COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 6, GFLAGS), + COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 7, GFLAGS), + COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, + RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(32), 0, GFLAGS), GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, RK3588_CLKGATE_CON(34), 6, GFLAGS), + GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, + RK3588_CLKGATE_CON(32), 8, GFLAGS), GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, RK3588_CLKGATE_CON(34), 7, GFLAGS), GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, @@ -1531,21 +1528,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(37), 1, GFLAGS), GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, RK3588_CLKGATE_CON(37), 2, GFLAGS), - COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, - RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(32), 0, GFLAGS), GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, RK3588_CLKGATE_CON(32), 3, GFLAGS), GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, RK3588_CLKGATE_CON(32), 4, GFLAGS), - COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(32), 6, GFLAGS), - COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, - RK3588_CLKGATE_CON(32), 7, GFLAGS), - GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, - RK3588_CLKGATE_CON(32), 8, GFLAGS), GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, RK3588_CLKGATE_CON(32), 10, GFLAGS), GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, @@ -1580,30 +1566,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, RK3588_CLKGATE_CON(35), 10, GFLAGS), - GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, - RK3588_CLKGATE_CON(38), 3, GFLAGS), - GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, - RK3588_CLKGATE_CON(38), 4, GFLAGS), - GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, - RK3588_CLKGATE_CON(38), 5, GFLAGS), - GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, - RK3588_CLKGATE_CON(38), 6, GFLAGS), - GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, - RK3588_CLKGATE_CON(38), 7, GFLAGS), - GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, - RK3588_CLKGATE_CON(38), 8, GFLAGS), - GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, - RK3588_CLKGATE_CON(38), 9, GFLAGS), - GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, - RK3588_CLKGATE_CON(38), 13, GFLAGS), - GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, - RK3588_CLKGATE_CON(38), 14, GFLAGS), - GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, - RK3588_CLKGATE_CON(38), 15, GFLAGS), - GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, - RK3588_CLKGATE_CON(39), 0, GFLAGS), - GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, - RK3588_CLKGATE_CON(39), 1, GFLAGS), GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, @@ -1614,10 +1576,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), /* rga */ - GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, - RK3588_CLKGATE_CON(76), 4, GFLAGS), - GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, - RK3588_CLKGATE_CON(76), 5, GFLAGS), COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(76), 6, GFLAGS), @@ -1627,6 +1585,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, RK3588_CLKGATE_CON(76), 1, GFLAGS), + GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 4, GFLAGS), + GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 5, GFLAGS), /* vdec */ COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, @@ -1638,10 +1600,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(40), 2, GFLAGS), - GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, - RK3588_CLKGATE_CON(40), 3, GFLAGS), - GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, - RK3588_CLKGATE_CON(40), 4, GFLAGS), COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(40), 7, GFLAGS), @@ -1657,10 +1615,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(41), 1, GFLAGS), - GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, - RK3588_CLKGATE_CON(41), 2, GFLAGS), - GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, - RK3588_CLKGATE_CON(41), 3, GFLAGS), COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(41), 6, GFLAGS), @@ -1675,17 +1629,12 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, RK3588_CLKGATE_CON(75), 0, GFLAGS), - GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, - RK3588_CLKGATE_CON(75), 2, GFLAGS), COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, RK3588_CLKGATE_CON(75), 3, GFLAGS), MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), - MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), - MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), - /* usb */ COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, @@ -1693,53 +1642,41 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, RK3588_CLKGATE_CON(42), 1, GFLAGS), - GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, - RK3588_CLKGATE_CON(42), 10, GFLAGS), - GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, - RK3588_CLKGATE_CON(42), 11, GFLAGS), - GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, - RK3588_CLKGATE_CON(42), 12, GFLAGS), - GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, - RK3588_CLKGATE_CON(42), 13, GFLAGS), - GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, - RK3588_CLKGATE_CON(42), 4, GFLAGS), GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, RK3588_CLKGATE_CON(42), 5, GFLAGS), GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, RK3588_CLKGATE_CON(42), 6, GFLAGS), - GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, - RK3588_CLKGATE_CON(42), 7, GFLAGS), GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, RK3588_CLKGATE_CON(42), 8, GFLAGS), GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, RK3588_CLKGATE_CON(42), 9, GFLAGS), /* vdpu */ + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 2, GFLAGS), + COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 3, GFLAGS), GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(45), 4, GFLAGS), - GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, - RK3588_CLKGATE_CON(45), 5, GFLAGS), COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, RK3588_CLKGATE_CON(45), 6, GFLAGS), - GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, - RK3588_CLKGATE_CON(44), 10, GFLAGS), GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 11, GFLAGS), - GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, - RK3588_CLKGATE_CON(44), 12, GFLAGS), GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 13, GFLAGS), - GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, - RK3588_CLKGATE_CON(44), 14, GFLAGS), GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 15, GFLAGS), - GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, - RK3588_CLKGATE_CON(45), 0, GFLAGS), GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(45), 1, GFLAGS), - GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, - RK3588_CLKGATE_CON(45), 2, GFLAGS), GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(45), 3, GFLAGS), GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, @@ -1756,24 +1693,16 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, RK3588_CLKGATE_CON(45), 12, GFLAGS), - COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, - RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(44), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, - RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, - RK3588_CLKGATE_CON(44), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, - RK3588_CLKGATE_CON(44), 2, GFLAGS), - COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, - RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(44), 3, GFLAGS), - GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, - RK3588_CLKGATE_CON(44), 8, GFLAGS), GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 9, GFLAGS), /* venc */ + COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(48), 0, GFLAGS), + COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(48), 1, GFLAGS), COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, RK3588_CLKGATE_CON(47), 0, GFLAGS), @@ -1787,21 +1716,20 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(47), 6, GFLAGS), - COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(48), 0, GFLAGS), - COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, - RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(48), 1, GFLAGS), - GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, - RK3588_CLKGATE_CON(48), 4, GFLAGS), - GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, - RK3588_CLKGATE_CON(48), 5, GFLAGS), COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(48), 6, GFLAGS), /* vi */ + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 2, GFLAGS), COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, RK3588_CLKGATE_CON(51), 10, GFLAGS), @@ -1846,15 +1774,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(49), 12, GFLAGS), GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, RK3588_CLKGATE_CON(49), 13, GFLAGS), - COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, - RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(49), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, - RK3588_CLKGATE_CON(49), 1, GFLAGS), - COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, - RK3588_CLKGATE_CON(49), 2, GFLAGS), COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(49), 6, GFLAGS), @@ -1864,32 +1783,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(49), 8, GFLAGS), /* vo0 */ - GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, - RK3588_CLKGATE_CON(56), 4, GFLAGS), - GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, - RK3588_CLKGATE_CON(56), 5, GFLAGS), - GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, - RK3588_CLKGATE_CON(56), 6, GFLAGS), - GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, - RK3588_CLKGATE_CON(56), 7, GFLAGS), - GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, - RK3588_CLKGATE_CON(56), 8, GFLAGS), - GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, - RK3588_CLKGATE_CON(56), 9, GFLAGS), - GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, - RK3588_CLKGATE_CON(55), 11, GFLAGS), - GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, - RK3588_CLKGATE_CON(55), 12, GFLAGS), - GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, - RK3588_CLKGATE_CON(55), 13, GFLAGS), - GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, - RK3588_CLKGATE_CON(55), 14, GFLAGS), - GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, - RK3588_CLKGATE_CON(56), 10, GFLAGS), - GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, - RK3588_CLKGATE_CON(56), 0, GFLAGS), - GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, - RK3588_CLKGATE_CON(56), 1, GFLAGS), COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(55), 0, GFLAGS), @@ -1905,6 +1798,26 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, RK3588_CLKGATE_CON(55), 4, GFLAGS), + GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 4, GFLAGS), + GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 5, GFLAGS), + GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 6, GFLAGS), + GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 7, GFLAGS), + GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 8, GFLAGS), + GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 9, GFLAGS), + GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(55), 11, GFLAGS), + GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(55), 14, GFLAGS), + GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 0, GFLAGS), + GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 1, GFLAGS), GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, @@ -1916,8 +1829,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_i2s4_8ch_tx_fracmux, RK3588_FRAC_MAX_PRATE), GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, RK3588_CLKGATE_CON(56), 13, GFLAGS), - GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, - RK3588_CLKGATE_CON(56), 14, GFLAGS), COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(56), 15, GFLAGS), @@ -1927,8 +1838,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_i2s8_8ch_tx_fracmux, RK3588_FRAC_MAX_PRATE), GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, RK3588_CLKGATE_CON(57), 1, GFLAGS), - GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, - RK3588_CLKGATE_CON(57), 2, GFLAGS), COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(57), 3, GFLAGS), @@ -1940,8 +1849,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(57), 5, GFLAGS), GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, RK3588_CLKGATE_CON(57), 6, GFLAGS), - GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, - RK3588_CLKGATE_CON(57), 7, GFLAGS), COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(57), 8, GFLAGS), @@ -1961,6 +1868,47 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(56), 3, GFLAGS), /* vo1 */ + COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 9, GFLAGS), + COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, + RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 0, GFLAGS), + COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, + RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 4, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 5, GFLAGS), + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 3, GFLAGS), + COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(74), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(74), 2, GFLAGS), + MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, RK3588_CLKGATE_CON(62), 0, GFLAGS), GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, @@ -1977,10 +1925,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(62), 5, GFLAGS), GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, RK3588_CLKGATE_CON(60), 4, GFLAGS), - GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, - RK3588_CLKGATE_CON(60), 5, GFLAGS), - GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, - RK3588_CLKGATE_CON(60), 6, GFLAGS), GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, RK3588_CLKGATE_CON(60), 7, GFLAGS), GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, @@ -2012,31 +1956,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(61), 6, GFLAGS), GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, RK3588_CLKGATE_CON(61), 7, GFLAGS), - COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, - RK3588_CLKGATE_CON(65), 9, GFLAGS), GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, RK3588_CLKGATE_CON(60), 9, GFLAGS), GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, RK3588_CLKGATE_CON(60), 10, GFLAGS), - COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, - RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(59), 0, GFLAGS), - COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, - RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, - RK3588_CLKGATE_CON(59), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, - RK3588_CLKGATE_CON(59), 2, GFLAGS), - COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, - RK3588_CLKGATE_CON(59), 3, GFLAGS), - COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, - RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, - RK3588_CLKGATE_CON(59), 4, GFLAGS), - COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, - RK3588_CLKGATE_CON(59), 5, GFLAGS), GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, @@ -2045,8 +1968,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(59), 15, GFLAGS), GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, RK3588_CLKGATE_CON(65), 8, GFLAGS), - GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, - RK3588_CLKGATE_CON(65), 4, GFLAGS), COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(65), 5, GFLAGS), @@ -2056,8 +1977,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_i2s10_8ch_rx_fracmux, RK3588_FRAC_MAX_PRATE), GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, RK3588_CLKGATE_CON(65), 7, GFLAGS), - GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, - RK3588_CLKGATE_CON(60), 0, GFLAGS), COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, RK3588_CLKGATE_CON(60), 1, GFLAGS), @@ -2067,8 +1986,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_i2s7_8ch_rx_fracmux, RK3588_FRAC_MAX_PRATE), GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, RK3588_CLKGATE_CON(60), 3, GFLAGS), - GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, - RK3588_CLKGATE_CON(65), 0, GFLAGS), COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, RK3588_CLKGATE_CON(65), 1, GFLAGS), @@ -2087,8 +2004,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_i2s5_8ch_tx_fracmux, RK3588_FRAC_MAX_PRATE), GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, RK3588_CLKGATE_CON(62), 8, GFLAGS), - GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, - RK3588_CLKGATE_CON(62), 12, GFLAGS), COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, RK3588_CLKGATE_CON(62), 13, GFLAGS), @@ -2109,10 +2024,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(63), 2, GFLAGS), MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), - GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, - RK3588_CLKGATE_CON(63), 3, GFLAGS), - GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, - RK3588_CLKGATE_CON(63), 4, GFLAGS), COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, RK3588_CLKGATE_CON(63), 5, GFLAGS), @@ -2122,8 +2033,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_spdif3_fracmux, RK3588_FRAC_MAX_PRATE), GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, RK3588_CLKGATE_CON(63), 7, GFLAGS), - GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, - RK3588_CLKGATE_CON(63), 8, GFLAGS), COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(63), 9, GFLAGS), @@ -2133,27 +2042,15 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { &rk3588_spdif4_fracmux, RK3588_FRAC_MAX_PRATE), GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, RK3588_CLKGATE_CON(63), 11, GFLAGS), - GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, - RK3588_CLKGATE_CON(63), 12, GFLAGS), COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(63), 13, GFLAGS), - GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, - RK3588_CLKGATE_CON(63), 14, GFLAGS), COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(63), 15, GFLAGS), - GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, - RK3588_CLKGATE_CON(64), 0, GFLAGS), COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(64), 1, GFLAGS), - COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(74), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, - RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, - RK3588_CLKGATE_CON(74), 2, GFLAGS), GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, RK3588_CLKGATE_CON(73), 12, GFLAGS), GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, @@ -2166,18 +2063,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(72), 2, GFLAGS), GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, RK3588_CLKGATE_CON(72), 4, GFLAGS), - COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_aupll_npll_spll_p, 0, - RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(52), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, - RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, - RK3588_CLKGATE_CON(52), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, - RK3588_CLKGATE_CON(52), 2, GFLAGS), - COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, - RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, - RK3588_CLKGATE_CON(52), 3, GFLAGS), GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, RK3588_CLKGATE_CON(52), 8, GFLAGS), GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, @@ -2217,8 +2102,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(53), 8, GFLAGS), GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, RK3588_CLKGATE_CON(53), 10, GFLAGS), - MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, - RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(2), 8, GFLAGS), GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, @@ -2247,6 +2130,32 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), /* pmu */ + COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, @@ -2285,32 +2194,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), - COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, - RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, - RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), - COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, - RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, - RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), - COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, - RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, - RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), - COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, - RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, - RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), - COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, - RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, - RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), - COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, - RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, - RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), - COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, - RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, - RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), - GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, - RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, - RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, - RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, @@ -2372,6 +2255,123 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, CLK_IS_CRITICAL, RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), + + GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 12, GFLAGS), + GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 14, GFLAGS), + GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, + RK3588_CLKGATE_CON(64), 0, GFLAGS), + GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 8, GFLAGS), + GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 4, GFLAGS), + GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 3, GFLAGS), + GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(62), 12, GFLAGS), + GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 0, GFLAGS), + GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 0, GFLAGS), + GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 4, GFLAGS), + GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, + RK3588_CLKGATE_CON(60), 5, GFLAGS), + GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 6, GFLAGS), + GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 7, GFLAGS), + GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 2, GFLAGS), + GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 14, GFLAGS), + GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 10, GFLAGS), + GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, + RK3588_CLKGATE_CON(55), 12, GFLAGS), + GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(55), 13, GFLAGS), + GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 4, GFLAGS), + GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 5, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 8, GFLAGS), + GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 5, GFLAGS), + GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 10, GFLAGS), + GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 12, GFLAGS), + GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 14, GFLAGS), + GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 0, GFLAGS), + GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, + RK3588_CLKGATE_CON(45), 2, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 7, GFLAGS), + GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 10, GFLAGS), + GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 11, GFLAGS), + GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 12, GFLAGS), + GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 13, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 4, GFLAGS), + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, + RK3588_CLKGATE_CON(75), 2, GFLAGS), + GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 2, GFLAGS), + GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 3, GFLAGS), + GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 3, GFLAGS), + GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 4, GFLAGS), + GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, + RK3588_CLKGATE_CON(39), 0, GFLAGS), + GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, + RK3588_CLKGATE_CON(39), 1, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 3, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 4, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 5, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 6, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 7, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 8, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 9, GFLAGS), + GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, + RK3588_CLKGATE_CON(38), 13, GFLAGS), + GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, + RK3588_CLKGATE_CON(38), 14, GFLAGS), + GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, + RK3588_CLKGATE_CON(38), 15, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 10, GFLAGS), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 11, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 4, GFLAGS), + GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 5, GFLAGS), + GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 7, GFLAGS), + GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 5, GFLAGS), + GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 2, GFLAGS), }; static void __iomem *rk3588_cru_base;