From dbf5dc2bc487c92df9d1f1aae90ef9b3f6f34be3 Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Thu, 21 Nov 2024 14:40:07 +0800
Subject: [PATCH] arm64: dts: rockchip: Add rtc node for rv1126b

Change-Id: Ib3b8eebcedda047c35bbd72fc62b37eda511c859
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 372d64661d24..fd16a690ef47 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -178,6 +178,11 @@
 			<49152000>;
 	};
 
+	grf: syscon@20100000 {
+		compatible = "rockchip,rv1126b-grf", "syscon";
+		reg = <0x20100000 0x91000>;
+	};
+
 	ioc_grf: syscon@201a0000 {
 		compatible = "rockchip,rv1126b-ioc-grf", "syscon";
 		reg = <0x201a0000 0x50000>;
@@ -373,6 +378,18 @@
 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	rtc: rtc@21280000 {
+		compatible = "rockchip,rv1126b-rtc";
+		reg = <0x21280000 0x1000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_RTC_ROOT>;
+		clock-names = "pclk_phy";
+		assigned-clocks = <&cru PCLK_RTC_ROOT>;
+		assigned-clock-rates = <50000000>;
+		status = "disabled";
+	};
+
 	emmc: mmc@21470000 {
 		compatible = "rockchip,rv1126b-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x21470000 0x4000>;