From dc539d24551377eed3320b41db6ace4ab18d0ea9 Mon Sep 17 00:00:00 2001 From: William Wu Date: Mon, 5 Nov 2018 12:07:57 +0800 Subject: [PATCH] phy: rockchip-inno-combphy: tuning lane 0 TX driver swing This patch tuning lane 0 TX driver swing for USB 3.0 to get larger swing for LFPS. Change-Id: I97d0cea4da86110fed349c07728366640346f7a8 Signed-off-by: William Wu --- drivers/phy/rockchip/phy-rockchip-inno-combphy.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c index 4ca7f95573e9..4ed7f5d24e0d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c @@ -611,7 +611,15 @@ static int rk1808_combphy_cfg(struct rockchip_combphy_priv *priv) writel(reg, priv->mmio + 0x2000); } - /* Tuning Tx */ + /* + * Tuning Tx: + * offset 0x21b8 bit[7:4]: lane 0 TX driver swing + * tuning bits with weight, "1111" represents the + * largest swing and "0000" the smallest. + */ + reg = readl(priv->mmio + 0x21b8); + reg = (reg & ~0xf0) | 0xa0; + writel(reg, priv->mmio + 0x21b8); /* * Tuning Rx for RJTL: