From dc6751a0270e235d92a915c877e0ef3ebdbd089b Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 7 Dec 2020 09:19:14 +0800 Subject: [PATCH] clk: rockchip: rk3568: add CLK_SET_RATE_NO_REPARENT flag for rkvdec Signed-off-by: Elaine Zhang Change-Id: I2126cd5833319dfdd097259a340d4c21480e4c4d --- drivers/clk/rockchip/clk-rk3568.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index a9cfa187b19b..9d0c23f0abb1 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -334,8 +334,8 @@ PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; -PNAME(aclk_rkvdec_pre_p) = { "gpll", "dummy_cpll" }; -PNAME(clk_rkvdec_core_p) = { "gpll", "dummy_cpll", "dummy_npll", "dummy_vpll" }; +PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; +PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; PNAME(clk_32k_ioe_p) = { "clk_rtc_32k", "xin32k" }; static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { @@ -1180,7 +1180,7 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(24), 8, GFLAGS), - COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, 0, + COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 0, GFLAGS), COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, @@ -1193,7 +1193,7 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 6, GFLAGS), - COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, 0, + COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3568_CLKGATE_CON(25), 7, GFLAGS), COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0,