From dc6b7b171521e77ed29ad50cdfaf6b92ccd50f6f Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 9 Jun 2025 16:22:48 +0800 Subject: [PATCH] arm64: dts: rockchip: rv1126b: add clk_cpll_div10 assigned clk rate Change-Id: I2fdedc4ebd266082ac09514c5749f509f5a9cb2b Signed-off-by: Elaine Zhang --- arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi index e95de72f9d2c..6ffd83cb94c3 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi @@ -940,7 +940,8 @@ <&cru CLK_UART_FRAC0>, <&cru CLK_UART_FRAC1>, <&cru CLK_CM_FRAC0>, <&cru CLK_CM_FRAC1>, <&cru CLK_CM_FRAC2>, <&cru CLK_AUDIO_FRAC0>, - <&cru CLK_AUDIO_FRAC1>; + <&cru CLK_AUDIO_FRAC1>, <&cru CLK_AISP_PLL>, + <&cru CLK_CPLL_DIV10>; assigned-clock-rates = <1188000000>, <1000000000>, <786432000>, <786432000>, @@ -950,7 +951,8 @@ <96000000>, <128000000>, <18432000>, <500000000>, <32768000>, <45158400>, - <49152000>; + <49152000>, <393216000>, + <98304000>; }; grf: syscon@20100000 {