diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 4f6663c05066..2322c3f04238 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -1,8 +1,49 @@ # SPDX-License-Identifier: GPL-2.0 +# common clock support for ROCKCHIP SoC family. +config COMMON_CLK_ROCKCHIP + tristate "Rockchip clock controller common support" + depends on ARCH_ROCKCHIP + default ARCH_ROCKCHIP + help + Say y here to enable common clock controller for Rockchip platforms. + +if COMMON_CLK_ROCKCHIP config ROCKCHIP_CLK_COMPENSATION bool "Rockchip Clk Compensation" help Say y here to enable clk compensation(+/- 1000 ppm). +config ROCKCHIP_CLK_BOOST + bool "Rockchip Clk Boost" + default y if CPU_PX30 + help + Say y here to enable clk boost. + +config ROCKCHIP_DDRCLK_SCPI + bool "Rockchip DDR Clk SCPI" + default y if RK3368_SCPI_PROTOCOL + help + Say y here to enable ddr clk scpi. + +config ROCKCHIP_DDRCLK_SIP + bool "Rockchip DDR Clk SIP" + default y if CPU_RK3399 + help + Say y here to enable ddr clk sip. + +config ROCKCHIP_PLL_RK3066 + bool "Rockchip PLL Type RK3066" + default y if CPU_RK30XX || CPU_RK3188 || \ + CPU_RK3288 || CPU_RK3368 + help + Say y here to enable pll type is rk3066. + +config ROCKCHIP_PLL_RK3399 + bool "Rockchip PLL Type RK3399" + default y if CPU_RK3399 || CPU_RV110X + help + Say y here to enable pll type is rk3399. +endif + source "drivers/clk/rockchip/regmap/Kconfig" diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 12ff25a6db27..81f35c0d624d 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -174,7 +174,8 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, return -EINVAL; } - rockchip_boost_enable_recovery_sw_low(cpuclk->pll_hw); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_enable_recovery_sw_low(cpuclk->pll_hw); alt_prate = clk_get_rate(cpuclk->alt_parent); @@ -205,7 +206,8 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, } } - rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate); /* select alternate parent */ writel(HIWORD_UPDATE(reg_data->mux_core_alt, @@ -257,7 +259,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, if (ndata->old_rate > ndata->new_rate) rockchip_cpuclk_set_dividers(cpuclk, rate); - rockchip_boost_disable_recovery_sw(cpuclk->pll_hw); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_disable_recovery_sw(cpuclk->pll_hw); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; @@ -324,7 +327,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, cpuclk->reg_data = reg_data; cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; cpuclk->hw.init = &init; - if (reg_data->pll_name) { + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST) && reg_data->pll_name) { pll_clk = __clk_lookup(reg_data->pll_name); if (!pll_clk) { pr_err("%s: could not lookup pll clock: (%s)\n", diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 99deefa488a0..33d22e3fa124 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -338,12 +338,16 @@ rockchip_clk_register_ddrclk(const char *name, int flags, init.flags |= CLK_SET_RATE_NO_REPARENT; switch (ddr_flag) { +#ifdef CONFIG_ROCKCHIP_DDRCLK_SIP case ROCKCHIP_DDRCLK_SIP: init.ops = &rockchip_ddrclk_sip_ops; break; +#endif +#ifdef CONFIG_ROCKCHIP_DDRCLK_SCPI case ROCKCHIP_DDRCLK_SCPI: init.ops = &rockchip_ddrclk_scpi_ops; break; +#endif case ROCKCHIP_DDRCLK_SIP_V2: init.ops = &rockchip_ddrclk_sip_ops_v2; break; diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 96c3a4811ed9..19b0b7c6ff0d 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -56,12 +56,14 @@ struct rockchip_clk_pll { struct rockchip_clk_provider *ctx; +#ifdef CONFIG_ROCKCHIP_CLK_BOOST bool boost_enabled; u32 boost_backup_pll_usage; unsigned long boost_backup_pll_rate; unsigned long boost_low_rate; unsigned long boost_high_rate; struct regmap *boost; +#endif #ifdef CONFIG_DEBUG_FS struct hlist_node debug_node; #endif @@ -71,7 +73,15 @@ struct rockchip_clk_pll { #define to_rockchip_clk_pll_nb(nb) \ container_of(nb, struct rockchip_clk_pll, clk_nb) +#ifdef CONFIG_ROCKCHIP_CLK_BOOST static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll); +#ifdef CONFIG_DEBUG_FS +static HLIST_HEAD(clk_boost_list); +static DEFINE_MUTEX(clk_boost_lock); +#endif +#else +static inline void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) {} +#endif #define MHZ (1000UL * 1000UL) #define KHZ (1000UL) @@ -95,10 +105,6 @@ static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll); #define MAX_FOUTVCO_FREQ (2000 * MHZ) static struct rockchip_pll_rate_table auto_table; -#ifdef CONFIG_DEBUG_FS -static HLIST_HEAD(clk_boost_list); -static DEFINE_MUTEX(clk_boost_lock); -#endif int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel) { @@ -420,7 +426,7 @@ static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) return ret; } -static unsigned long +static unsigned long __maybe_unused rockchip_rk3036_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) { @@ -542,7 +548,8 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); - rockchip_boost_disable_low(pll); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_disable_low(pll); /* wait for the pll to lock */ ret = rockchip_rk3036_pll_wait_lock(pll); @@ -1365,18 +1372,22 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, else init.ops = &rockchip_rk3036_pll_clk_ops; break; +#ifdef CONFIG_ROCKCHIP_PLL_RK3066 case pll_rk3066: if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3066_pll_clk_norate_ops; else init.ops = &rockchip_rk3066_pll_clk_ops; break; +#endif +#ifdef CONFIG_ROCKCHIP_PLL_RK3399 case pll_rk3399: if (!pll->rate_table) init.ops = &rockchip_rk3399_pll_clk_norate_ops; else init.ops = &rockchip_rk3399_pll_clk_ops; break; +#endif default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, name); @@ -1408,6 +1419,7 @@ err_mux: return mux_clk; } +#ifdef CONFIG_ROCKCHIP_CLK_BOOST static unsigned long rockchip_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) { @@ -1717,4 +1729,5 @@ static int __init boost_debug_init(void) return 0; } late_initcall(boost_debug_init); -#endif +#endif /* CONFIG_DEBUG_FS */ +#endif /* CONFIG_ROCKCHIP_CLK_BOOST */