From dd0cb993becca72c8bcb71764b7aba167e971488 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 17 Aug 2021 17:36:31 +0800 Subject: [PATCH] clk: rockchip: optimize static memory consume ./scripts/bloat-o-meter clk-pll_old.o clk-pll.o add/remove: 3/36 grow/shrink: 3/3 up/down: 1832/-7395 (-5563) Function old new delta rockchip_pll_clk_set_by_auto.constprop - 908 +908 rockchip_rk3066_pll_clk_set_by_auto.constprop - 508 +508 rockchip_rk3036_pll_init 236 416 +180 rockchip_rk3036_pll_set_rate 80 228 +148 rockchip_rk3036_pll_get_params - 72 +72 rockchip_rk3036_pll_recalc_rate 336 352 +16 clk_boost_list 4 - -4 __initcall_boost_debug_init7 4 - -4 clk_boost_lock 20 - -20 boost_summary_open 20 - -20 boost_config_open 20 - -20 rockchip_rk3399_pll_is_enabled 24 - -24 rockchip_rk3399_pll_disable 24 - -24 rockchip_rk3066_pll_is_enabled 24 - -24 rockchip_rk3066_pll_disable 24 - -24 rockchip_rk3399_pll_enable 32 - -32 rockchip_rk3066_pll_enable 32 - -32 rockchip_rk3036_pll_set_params 376 344 -32 rockchip_boost_disable_recovery_sw 64 - -64 boost_config_show 76 - -76 rockchip_rk3399_pll_clk_ops 104 - -104 rockchip_rk3399_pll_clk_norate_ops 104 - -104 rockchip_rk3066_pll_clk_ops 104 - -104 rockchip_rk3066_pll_clk_norate_ops 104 - -104 rockchip_rk3399_pll_set_rate 108 - -108 rockchip_rk3399_pll_wait_lock 116 - -116 rockchip_rk3066_pll_set_rate 120 - -120 rockchip_boost_add_core_div 120 - -120 rockchip_clk_register_pll 1124 1000 -124 rockchip_boost_enable_recovery_sw_low 144 - -144 rockchip_rk3066_pll_init 156 - -156 boost_summary_fops 160 - -160 boost_config_fops 160 - -160 rockchip_rk3066_pll_recalc_rate 172 - -172 rockchip_pll_wait_lock 236 - -236 rockchip_rk3399_pll_init 240 - -240 rockchip_pll_con_to_rate 252 - -252 __func__ 404 141 -263 rockchip_rk3399_pll_recalc_rate 288 - -288 boost_debug_init 316 - -316 rockchip_rk3399_pll_set_params 392 - -392 boost_summary_show 404 - -404 rockchip_rk3066_pll_set_params 436 - -436 rockchip_boost_init 864 - -864 rockchip_get_pll_settings 1508 - -1508 Total: Before=10678, After=5115, chg -52.10% ./scripts/bloat-o-meter clk-cpu_old.o clk-cpu.o add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-72 (-72) Function old new delta rockchip_cpuclk_notifier_cb 1716 1700 -16 rockchip_clk_register_cpuclk 728 672 -56 Total: Before=2694, After=2622, chg -2.67% ./scripts/bloat-o-meter clk-ddr_old.o clk-ddr.o add/remove: 0/9 grow/shrink: 0/1 up/down: 0/-780 (-780) Function old new delta ddr_clk_cached 4 - -4 rockchip_clk_register_ddrclk 352 312 -40 rockchip_ddrclk_scpi_recalc_rate 44 - -44 rockchip_ddrclk_scpi_round_rate 48 - -48 rockchip_ddrclk_scpi_set_rate 96 - -96 rockchip_ddrclk_sip_ops 104 - -104 rockchip_ddrclk_scpi_ops 104 - -104 rockchip_ddrclk_sip_round_rate 108 - -108 rockchip_ddrclk_sip_recalc_rate 112 - -112 rockchip_ddrclk_sip_set_rate 120 - -120 Total: Before=1761, After=981, chg -44.29% Signed-off-by: Elaine Zhang Change-Id: I469229b9566af1cab6cc3a6bb9f4f8e308e0eded --- drivers/clk/rockchip/Kconfig | 41 ++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk-cpu.c | 11 +++++---- drivers/clk/rockchip/clk-ddr.c | 4 ++++ drivers/clk/rockchip/clk-pll.c | 27 ++++++++++++++++------ 4 files changed, 72 insertions(+), 11 deletions(-) diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 4f6663c05066..2322c3f04238 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -1,8 +1,49 @@ # SPDX-License-Identifier: GPL-2.0 +# common clock support for ROCKCHIP SoC family. +config COMMON_CLK_ROCKCHIP + tristate "Rockchip clock controller common support" + depends on ARCH_ROCKCHIP + default ARCH_ROCKCHIP + help + Say y here to enable common clock controller for Rockchip platforms. + +if COMMON_CLK_ROCKCHIP config ROCKCHIP_CLK_COMPENSATION bool "Rockchip Clk Compensation" help Say y here to enable clk compensation(+/- 1000 ppm). +config ROCKCHIP_CLK_BOOST + bool "Rockchip Clk Boost" + default y if CPU_PX30 + help + Say y here to enable clk boost. + +config ROCKCHIP_DDRCLK_SCPI + bool "Rockchip DDR Clk SCPI" + default y if RK3368_SCPI_PROTOCOL + help + Say y here to enable ddr clk scpi. + +config ROCKCHIP_DDRCLK_SIP + bool "Rockchip DDR Clk SIP" + default y if CPU_RK3399 + help + Say y here to enable ddr clk sip. + +config ROCKCHIP_PLL_RK3066 + bool "Rockchip PLL Type RK3066" + default y if CPU_RK30XX || CPU_RK3188 || \ + CPU_RK3288 || CPU_RK3368 + help + Say y here to enable pll type is rk3066. + +config ROCKCHIP_PLL_RK3399 + bool "Rockchip PLL Type RK3399" + default y if CPU_RK3399 || CPU_RV110X + help + Say y here to enable pll type is rk3399. +endif + source "drivers/clk/rockchip/regmap/Kconfig" diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 12ff25a6db27..81f35c0d624d 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -174,7 +174,8 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, return -EINVAL; } - rockchip_boost_enable_recovery_sw_low(cpuclk->pll_hw); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_enable_recovery_sw_low(cpuclk->pll_hw); alt_prate = clk_get_rate(cpuclk->alt_parent); @@ -205,7 +206,8 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, } } - rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate); /* select alternate parent */ writel(HIWORD_UPDATE(reg_data->mux_core_alt, @@ -257,7 +259,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, if (ndata->old_rate > ndata->new_rate) rockchip_cpuclk_set_dividers(cpuclk, rate); - rockchip_boost_disable_recovery_sw(cpuclk->pll_hw); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_disable_recovery_sw(cpuclk->pll_hw); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; @@ -324,7 +327,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, cpuclk->reg_data = reg_data; cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; cpuclk->hw.init = &init; - if (reg_data->pll_name) { + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST) && reg_data->pll_name) { pll_clk = __clk_lookup(reg_data->pll_name); if (!pll_clk) { pr_err("%s: could not lookup pll clock: (%s)\n", diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 99deefa488a0..33d22e3fa124 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -338,12 +338,16 @@ rockchip_clk_register_ddrclk(const char *name, int flags, init.flags |= CLK_SET_RATE_NO_REPARENT; switch (ddr_flag) { +#ifdef CONFIG_ROCKCHIP_DDRCLK_SIP case ROCKCHIP_DDRCLK_SIP: init.ops = &rockchip_ddrclk_sip_ops; break; +#endif +#ifdef CONFIG_ROCKCHIP_DDRCLK_SCPI case ROCKCHIP_DDRCLK_SCPI: init.ops = &rockchip_ddrclk_scpi_ops; break; +#endif case ROCKCHIP_DDRCLK_SIP_V2: init.ops = &rockchip_ddrclk_sip_ops_v2; break; diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 96c3a4811ed9..19b0b7c6ff0d 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -56,12 +56,14 @@ struct rockchip_clk_pll { struct rockchip_clk_provider *ctx; +#ifdef CONFIG_ROCKCHIP_CLK_BOOST bool boost_enabled; u32 boost_backup_pll_usage; unsigned long boost_backup_pll_rate; unsigned long boost_low_rate; unsigned long boost_high_rate; struct regmap *boost; +#endif #ifdef CONFIG_DEBUG_FS struct hlist_node debug_node; #endif @@ -71,7 +73,15 @@ struct rockchip_clk_pll { #define to_rockchip_clk_pll_nb(nb) \ container_of(nb, struct rockchip_clk_pll, clk_nb) +#ifdef CONFIG_ROCKCHIP_CLK_BOOST static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll); +#ifdef CONFIG_DEBUG_FS +static HLIST_HEAD(clk_boost_list); +static DEFINE_MUTEX(clk_boost_lock); +#endif +#else +static inline void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) {} +#endif #define MHZ (1000UL * 1000UL) #define KHZ (1000UL) @@ -95,10 +105,6 @@ static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll); #define MAX_FOUTVCO_FREQ (2000 * MHZ) static struct rockchip_pll_rate_table auto_table; -#ifdef CONFIG_DEBUG_FS -static HLIST_HEAD(clk_boost_list); -static DEFINE_MUTEX(clk_boost_lock); -#endif int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel) { @@ -420,7 +426,7 @@ static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) return ret; } -static unsigned long +static unsigned long __maybe_unused rockchip_rk3036_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) { @@ -542,7 +548,8 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); - rockchip_boost_disable_low(pll); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_disable_low(pll); /* wait for the pll to lock */ ret = rockchip_rk3036_pll_wait_lock(pll); @@ -1365,18 +1372,22 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, else init.ops = &rockchip_rk3036_pll_clk_ops; break; +#ifdef CONFIG_ROCKCHIP_PLL_RK3066 case pll_rk3066: if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3066_pll_clk_norate_ops; else init.ops = &rockchip_rk3066_pll_clk_ops; break; +#endif +#ifdef CONFIG_ROCKCHIP_PLL_RK3399 case pll_rk3399: if (!pll->rate_table) init.ops = &rockchip_rk3399_pll_clk_norate_ops; else init.ops = &rockchip_rk3399_pll_clk_ops; break; +#endif default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, name); @@ -1408,6 +1419,7 @@ err_mux: return mux_clk; } +#ifdef CONFIG_ROCKCHIP_CLK_BOOST static unsigned long rockchip_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) { @@ -1717,4 +1729,5 @@ static int __init boost_debug_init(void) return 0; } late_initcall(boost_debug_init); -#endif +#endif /* CONFIG_DEBUG_FS */ +#endif /* CONFIG_ROCKCHIP_CLK_BOOST */